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TPS82150SILT Datasheet(PDF) 10 Page - Texas Instruments |
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TPS82150SILT Datasheet(HTML) 10 Page - Texas Instruments |
10 / 27 page 4 R 4 R 3 R 2 R 1 R 2 R 64 . 0 V V 1 OUT 2 OUT + ´ + ´ » 10 TPS82150 SLVSDN4 – JUNE 2017 www.ti.com Product Folder Links: TPS82150 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Device Functional Modes (continued) When the SS/TR pin voltage is between 50 mV and 1.2 V, the VOUT2 tracks the VOUT1 as described in Equation 5. space (5) space When the SS/TR pin voltage is above 1.2 V, the voltage tracking is disabled and the FB pin voltage is regulated at 0.8 V. For decreasing SS/TR pin voltage, the device doesn't sink current from the output. So the resulting decreases of the output voltage may be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN+0.3V. Details about tracking and sequencing circuits are found in SLVA470. 7.4.4 Power Good Output (PG) The device has a power good (PG) output. The PG pin goes high impedance once the output is above 95% of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage. The PG pin is an open drain output and is specified to sink up to 2mA. The power good output requires a pull-up resistor connecting to any voltage rail less than 6V. The PG pin goes low when the device is in shutdown or thermal shutdown. When the device is in UVLO, the PG pin is high impedance. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin floating when it is not used. Table 1 shows the PG pin logic. Table 1. Power Good Pin Logic Device State PG Logic Status High Impedance Low Enable (EN=High) VFB ≥ VTH_PG √ VFB ≤ VTH_PG √ Shutdown (EN=Low) √ UVLO 0.7 V < VIN < VUVLO √ Thermal Shutdown TJ > TSD √ Power Supply Removal VIN < 0.7 V √ |
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