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X9259TB24I-2.7 Datasheet(PDF) 3 Page - Xicor Inc. |
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X9259TB24I-2.7 Datasheet(HTML) 3 Page - Xicor Inc. |
3 / 25 page X9259 Characteristics subject to change without notice. 3 of 25 REV 1.2.3 4/30/02 www.xicor.com PIN CONFIGURATION PIN ASSIGNMENTS Note 1: A0-A3 Device address pins must be tie to a logic level. Pin (SOIC/TSSOP) Pin (XBGA) Symbol Function 2 F2 A0 Device Address for 2-Wire bus. (See Note 1) 3F1 RW3 Wiper Terminal for Potentiometer 3. 4D2 RH3 High Terminal for Potentiometer 3. 5E1 RL3 Low Terminal for Potentiometer 3. 6 E2 NC1 Must be left unconnected 7C1 VCC System Supply Voltage 8B1 RL0 Low Terminal for Potentiometer 0. 9C2 RH0 High Terminal for Potentiometer 0. 10 A1 RW0 Wiper Terminal for Potentiometer 0. 11 A2 A2 Device Address for 2-Wire bus. (See Note 1) 12 B2 WP Hardware Write Protect 13 B3 SDA Serial Data Input/Output for 2-Wire bus. 14 A3 A1 Device Address for 2-Wire bus. (See Note 1) 15 A4 RL1 Low Terminal for Potentiometer 1. 16 C3 RH1 High Terminal for Potentiometer 1. 17 B4 RW1 Wiper Terminal for Potentiometer 1. 18 C4 VSS System Ground 20 E4 RW2 WiperTerminal for Potentiometer 2. 21 D3 RH2 High Terminal for Potentiometer 2. 22 F4 RL2 Low Terminal for Potentiometer 2. 23 F3 SCL Serial Clock for 2-Wire bus. 24 E3 A3 Device Address for 2-Wire Bus. (See Note 1) 6, 19 D1, D4 NC No Connect 1 E2 NC1 Must be left unconnected NC1 A0 RW3 NC VCC RL0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 A3 SCL RL2 RH2 RW2 NC VSS RW1 RH1 RL1 SOIC/TSSOP X9259 RH3 14 13 11 12 RL3 RH0 RW0 A2 A1 SDA WP 2 3 4 A B C D E F Top View–Bumps Down RW0 RL0 NC A0 A3 RL1 VCC RL3 RW3 NC1 SDA RW1 SCL RL2 WP NC RH0 RH1 RH3 VSS RW2 A2 A1 1 XBGA RH2 |
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