RX111_16 datasheet(88/127 Pages) RENESAS

Part #	RX111

Description	32 MHz 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory

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Manufacturer	RENESAS [Renesas Technology Corp]

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R01DS0190EJ0130 Rev.1.30

Page 88 of 127

May 31, 2016

RX111 Group

5. Electrical Characteristics

Note 1. tPcyc: PCLK cycle

Table 5.34

Timing of On-Chip Peripheral Modules (3)

Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVSS0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V,

Ta = –40 to +105°C, C = 30 pF

Item

Symbol

Min.

Max.

Unit*1

Test Conditions

Simple

SPI

SCK clock cycle output (master)

tSPcyc

4

65536

tPcyc

Figure 5.46

SCK clock cycle input (slave)

6

65536

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise/fall time

tSPCKr, tSPCKf

—20

ns

Data input setup time (master)

2.7 V or above

tSU

65

—

ns

Figure 5.47,

Figure 5.49

1.8 V or above

95

—

Data input setup time (slave)

40

—

Data input hold time

tH

40

—

ns

SS input setup time

tLEAD

3—

tPcyc

SS input hold time

tLAG

3—

tPcyc

Data output delay time (master)

tOD

—40

ns

Data output delay time (slave)

2.7 V or above

—

65

1.8 V or above

—

85

Data output hold time (master)

2.7 V or above

tOH

–10

—

ns

1.8 V or above

–20

—

Data output hold time (slave)

–10

—

Data rise/fall time

tDr, tDf

—20

ns

SS input rise/fall time

tSSLr, tSSLf

—20

ns

Slave access time

tSA

—6

tPcyc

Figure 5.51,

Figure 5.52

Slave output release time

tREL

—6

tPcyc

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