S7G2 datasheet(63/116 Pages) RENESAS

Part #	S7G2

Description	32-bit ARM Cortex-M4 microcontroller

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Manufacturer	RENESAS [Renesas Technology Corp]

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R01DS0262EU0100 Rev.1.00

Page 63 of 113

Feb 23, 2016

S7G2

2. Electrical Characteristics

Note 1. tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.

Note 2. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation

is not guaranteed.

Note 3. The load is 30 pF.

Note 4. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.

Figure 2.26

I/O ports input timing

Figure 2.27

POEG input trigger timing

GPT32

Input capture pulse width

Single edge

tGTICW

1.5

-

tPDcyc

Figure 2.28

Dual edge

2.5

-

GTIOCxY_Z output skew

(x = 0 to 7, Y= A or B , Z = A or B)

Middle drive buffer

tGTISK*2 -4

ns

Figure 2.29

High drive buffer

-

4

GTIOCxY_Z output skew

(x = 8 to 13, Y = A or B, Z = A or B)

Middle drive buffer

-

4

High drive buffer

-

4

GTIOCxY_Z output skew

(x = 0 to 13, Y = A or B, Z = A or B)

Middle drive buffer

-

6

High drive buffer

-

6

OPS output skew

GTOUUP_x, GTOULO_x, GTOVUP_x,

GTOVLO_x, GTOWUP_x, GTOWLO_x

(x = A or B)

tGTOSK

*2

-5

ns

Figure 2.30

GPT(PWM

Delay

Generation

Circuit)

GTIOCxY_Z output skew

(x = 0 to 3, Y = A or B, Z = A)

tHRSK*3 -2.0

ns

Figure 2.31

AGT

AGTIO, AGTEE input cycle

tACYC*1 100

-

ns

Figure 2.32

AGTIO, AGTEE input high width, low width

tACKWH,

tACKWL

40

-

ns

AGTIO, AGTO, AGTOA, AGTOB output cycle

tACYC2

62.5

-

ns

ADC12

ADC12 trigger input pulse width

tTRGW

1.5

-

tPcyc

Figure 2.33

KINT

Key interrupt input low width

tKR

250

-

ns

Figure 2.34

Table 2.19

I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (2/2)

GPT32 Conditions:

Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: GTIOC6A_A, GTIOC6B_A,

GTIOC3A_B, GTIOC3B_B, GTIOC0A_B, GTIOC0B_B, GTIOC9A_B, GTIOC9B_B.

High drive output is selected in the port drive capability bit in the PmnPFS register for all other pins.

AGT Conditions:

Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Item

Symbol Min

Max

Unit

Test

conditions

Port

tPRW

POEG input trigger

tPOEW

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