S7G2 datasheet(86/116 Pages) RENESAS

Part #	S7G2

Description	32-bit ARM Cortex-M4 microcontroller

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Manufacturer	RENESAS [Renesas Technology Corp]

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86 / 116 page

R01DS0262EU0100 Rev.1.00

Page 86 of 113

Feb 23, 2016

S7G2

2. Electrical Characteristics

Figure 2.70

PDC AC timing

2.3.18

Graphics LCD Controller Timing

Note 1. Parallel RGB888, 666,565: Maximum 54 MHz

Serial RGB888: Maximum 60 MHz (4x speed)

Note 2. Use pins that have a letter appended to their names, for instance, “_A” or “_B”, to indicate

Note 3. Pins of group“_A” and “_B” combinations are used.

Figure 2.71

LCD_EXTCLK clock input timing

Table 2.33

Graphics LCD Controller timing

Conditions:

LCD_CLK: High drive output is selected in the port drive capability bit in the PmnPFS register.

LCD_DATA: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Item

Symbol

Min

Typ

Max

Unit

Test conditions

LCD_EXTCLK input clock frequency

tEcyc

-

60*1

MHz

Figure 2.71

LCD_EXTCLK input clock low pulse width

tWL

0.45

-

0.55

tEcyc

LCD_EXTCLK input clock high pulse width

tWH

0.45

-

0.55

LCD_CLK output clock frequency

tLcyc

-

60*1

MHz

Figure 2.72

LCD_CLK output clock low pulse width

tLOL

0.4

-

0.6

tLcyc

Figure 2.72

LCD_CLK output clock high pulse width

tLOH

0.4

-

0.6

tLcyc

Figure 2.72

LCD data output delay timing _A or _B combinations*2

tDD

–3.5

-

4

ns

Figure 2.73

_A and _B combinations*3

–5.0

-

5.5

LCD data output rise time (0.8 to 2.0 V)

tDr

--

2

Figure 2.74

LCD data output fall time (2.0 to 0.8 V)

tDf

--

2

PIXCLK

VSYNC

HSYNC

PIXD7 to PIXD0

tSYNCS

tPIXDS

tPIXDH

tSYNCH

1/2 Vcc

VIH VIH

VIL

tDcyc, tEcyc

tWH

tWL

LCD_EXTCLK

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