 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPD48288209AF1 Datasheet(PDF) 6 Page - Renesas Technology Corp |
|
||||||||||||||||||||||||||||||
UPD48288209AF1 Datasheet(HTML) 6 Page - Renesas Technology Corp |
|
|
6 / 54 page  µµµµPD48288209AF1, µµµµPD48288218AF1, µµµµPD48288236AF1 R10DS0254EJ0101 Rev. 1.01 Page 6 of 53 Jan. 15, 2016 Pin Description (1/2) Symbol Type Description CK, CK# Input Clock inputs: CK and CK# are differential clock inputs. This input clock pair registers address and control inputs on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK. CS# Input Chip select CS# enables the commands when CS# is LOW and disables them when CS# is HIGH. When the command is disabled, new commands are ignored, but internal operations continue. WE#, REF# Input WRITE command pin, Refresh command pin: WE#, REF# are sampled at the positive edge of CK, WE#, and REF# define (together with CS#) the command to be executed. A0–A20 Input Address inputs: A0–A20 define the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. In the x36 configuration, A19–A20 are reserved for address expansion; in the x18 configuration, A20 is reserved for address expansion. These expansion addresses can be treated as address inputs, but they do not affect the operation of the device. A21–A22 Input Reserved for future use: These signals should be tied to VSS or leave open. BA0–BA2 Input Bank address inputs; Select to which internal bank a command is being applied. DQ0–DQxx Input /Output Data input/output: The DQ signals form the 9/18/36 bit data bus. During READ commands, the data is referenced to both edges of QKx. During WRITE commands, the data is sampled at both edges of DKx. x 9 device uses DQ0 to DQ8. x18 device uses DQ0 to DQ17. x36 device uses DQ0 to DQ35. QKx, QKx# Output Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are always free running and edge- aligned with data output from the µPD48288209/18/36AF1. QKx# is ideally 180 degrees out of phase with QKx. For the x36 device, QK0 and QK0# are aligned with DQ0–DQ17. QK1 and QK1# are aligned with DQ18–DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0–DQ8. QK1 and QK1# are aligned with DQ9–DQ17. For the x9 device, QK0 and QK0# are aligned with DQ0–DQ8. DKx, DKx# Input Input data clock; DKx and DKx# are the differential input data clocks. All input data is referenced to both edges of DK. DK# is ideally 180 degrees out of phase with DK. For the x36 device, DQ0–DQ17 are referenced to DK0 and DK0#, and DQ18–DQ35 are referenced to DK1 and DK1#. For the x9 and x18 devices, all DQs are referenced to DK and DK#. DM Input Input data mask; The DM signal is the input mask signal for WRITE data. Input data is masked when DM is sampled HIGH along with the WRITE input data. DM is sampled on both edges of DK (DK1 for the x36 configuration). The signal should be VSS if not used. QVLD Output Data valid; The QVLD indicates valid output data. QVLD is edge-aligned with QKx and QKx#. |
Similar Part No. - UPD48288209AF1 |
|
Similar Description - UPD48288209AF1 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
