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HT82M9BEE Datasheet(PDF) 9 Page - Holtek Semiconductor Inc |
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HT82M9BEE Datasheet(HTML) 9 Page - Holtek Semiconductor Inc |
9 / 44 page HT82M9BEE/HT82M9BAE Rev. 1.50 9 December 22, 2008 Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions. The ALU provides the following functions: · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, opera- tions related to the status register may give different re- sults from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by exe- cuting the ²HALT² or ²CLR WDT² instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, upon entering the interrupt sequence or exe- cuting a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain inter- rupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the inter- rupt request will not be acknowledged, even if the re- lated interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be pre- vented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H I n d i r e c t A d d r e s s i n g R e g i s t e r 0 M P 0 I n d i r e c t A d d r e s s i n g R e g i s t e r 1 M P 1 B P A C C P C L T B L P T B L H W D T S S T A T U S I N T C T M R 0 T M R 0 C T M R 1 H T M R 1 L T M R 1 C P A P A C P B P B C P C P C C U S C U S R S C C T B H P P i p e _ c t r l A W R S T A L L S I E S M I S C E n d p t _ E N F I F O 0 F I F O 1 F I F O 2 F I F O 3 B a n k 1 1 9 H 4 2 H 4 3 H 4 4 H 4 5 H 4 6 H 4 7 H 4 8 H 4 9 H 4 1 H 4 A H 4 B H Bank 1 RAM Mapping |
Similar Part No. - HT82M9BEE_08 |
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Similar Description - HT82M9BEE_08 |
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