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74LVT162374DGG Datasheet(PDF) 10 Page - NXP Semiconductors |
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74LVT162374DGG Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 17 page 9397 750 14401 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 17 January 2005 10 of 17 Philips Semiconductors 74LVT162374 3.3 V 16-bit edge-triggered D-type flip-flop 12. Waveforms VM = 1.5 V; VI = GND to 3.0 V. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Propagation delay clock input to output, clock pulse width and maximum clock frequency VM = 1.5 V; VI = GND to 3.0 V. VOH is typical voltage output drop that occur with the output load. Fig 7. 3-state output enable time to HIGH-level and output disable time from HIGH-level VM = 1.5 V; VI = GND to 3.0 V. VOL is typical voltage output drop that occur with the output load. Fig 8. 3-state output enable time to LOW-level and output disable time from LOW-level 001aac373 tPHL tPLH tW(H) tW(L) 1/fmax VM VM VM VM VM nCP nQn 0 V 2.7 V VOH VOL nQn 001aac374 nOE VM tPZH tPHZ 0 V VOH − 0.3 V VM VM VOH 2.7 V 001aac375 tPZL tPLZ VOL + 0.3 V VM VM VM VOL 2.7 V 3.0 V nQn nOE |
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