ADC12L066CIVYX datasheet(10/27 Pages) NSC

Part #	ADC12L066CIVYX

Description	12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold

Download	27 Pages

Scroll/Zoom	100%

Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

Logo

10 / 27 page

Specification Definitions

APERTURE DELAY is the time after the rising edge of the

clock to when the input signal is acquired or held for conver-

sion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the

variation in aperture delay from sample to sample. Aperture

jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time that a repeti-

tive digital waveform is high to the total time of one period.

The specification here refers to the ADC clock input signal.

COMMON MODE VOLTAGE (V

CM)

is the d.c. potential

present at both signal inputs to the ADC.

CONVERSION LATENCY is the number of clock cycles

between initiation of conversion and when that data is pre-

sented to the output driver stage. Data for any given sample

is available at the output pins the Pipeline Delay plus the

Output Delay after the sample is taken. New data is available

at every clock cycle, but the data lags the conversion by the

pipeline delay.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /

6.02 and says that the converter is equivalent to a perfect

ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the

transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error − Offset Error

LSB (LEAST SIGNIFICANT BIT) is the bit that has the

smallest value or weight of all bits. This value is V

REF/2

n,

where “n” is the ADC resolution in bits, which is 12 in the

case of the ADC12DL066.

INTEGRAL NON LINEARITY (INL) is a measure of the

deviation of each individual code from a line drawn from

negative full scale (1⁄2 LSB below the first code transition)

through positive full scale (1⁄2 LSB above the last code

transition). The deviation of any given code from this straight

line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the second and third

order intermodulation products to the power in one of the

original frequencies. IMD is usually expressed in dBFS.

MISSING CODES are those output codes that will never

appear at the ADC outputs. The ADC12L066 is guaranteed

not to have any missing codes.

MSB (MOST SIGNIFICANT BIT) is the bit that has the

largest value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between

the input voltage (V

IN+ −VIN−) just causing a transition from

negative full scale to the first code and its ideal value of 0.5

LSB.

OFFSET ERROR is the input voltage that will cause a tran-

sition from a code of 01 1111 1111 to a code of 10 0000 0000.

OUTPUT DELAY is the time delay after the rising edge of

the clock before the data update is presented at the output

pins.

PIPELINE DELAY (LATENCY) See Conversion Latency

POSITIVE FULL SCALE ERROR is the difference between

the actual last code transition and its ideal value of 11⁄2 LSB

below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a mea-

sure of how well the ADC rejects a change in the power

supply voltage. For the ADC12L066, PSRR1 is the ratio of

the change in Full-Scale Error that results from a change in

the d.c. power supply voltage, expressed in dB. PSRR2 is a

measure of how well an a.c. signal riding upon the power

supply is rejected at the output.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the

sampling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)

Is the ratio, expressed in dB, of the rms value of the input

signal to the rms value of all of the other spectral compo-

nents below half the clock frequency, including harmonics

but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal, where a spurious signal

is any signal present in the output spectrum that is not

present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dBc, of the rms total of the first nine harmonic

levels at the output to the level of the fundamental at the

output. THD is calculated as

where f

1 is the RMS power of the fundamental (output)

frequency and f

2 through f10 are the RMS power in the first 9

harmonic frequencies.

SECOND HARMONIC DISTORTION (2ND HARM) is the

difference expressed in dB, between the RMS power in the

input frequency at the output and the power in its 2nd

harmonic level at the output.

THIRD HARMONIC DISTORTION (3RD HARM) is the dif-

ference, expressed in dB, between the RMS power in the

input frequency at the output and the power in its 3rd har-

monic level at the output.

www.national.com

10

Similar Part No. - ADC12L066CIVYX

Manufacturer	Part #	Datasheet	Description
National Semiconductor ...	ADC12L066CIVYX	1Mb / 27P	12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold

More results

Similar Description - ADC12L066CIVYX

Manufacturer	Part #	Datasheet	Description
National Semiconductor ...	ADC12L066	1Mb / 27P	12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold
	ADC11L066	742Kb / 27P	11-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold
	ADC12DL066	654Kb / 23P	Dual 12-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal Reference
Texas Instruments	ADC12DL066	804Kb / 31P	[Old version datasheet] Dual 12-Bit, 66 Msps, 450 MHz Input Bandwidth A/D Converter w/Internal Reference
Texas Instruments	ADC12040	1Mb / 29P	[Old version datasheet] 12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold
National Semiconductor ...	ADC12040	884Kb / 19P	12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold
Texas Instruments	ADC12040	1Mb / 30P	[Old version datasheet] 12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold
National Semiconductor ...	ADC12L080	1Mb / 23P	12-Bit, 80 MSPS, 450 MHz Bandwidth A/D Converter with Internal Reference
Texas Instruments	ADC12L080	987Kb / 28P	[Old version datasheet] 12-Bit, 80 MSPS, 450 MHz Bandwidth A/D Converter with Internal Reference
National Semiconductor ...	ADC12010	606Kb / 22P	12-Bit, 10 MSPS, 160 mW A/D Converter with Internal Sample-and-Hold

More results

ADC12L066CIVYX Datasheet(PDF) 10 Page - National Semiconductor (TI)

ADC12L066CIVYX Datasheet(HTML) 10 Page - National Semiconductor (TI)

Similar Part No. - ADC12L066CIVYX

Similar Description - ADC12L066CIVYX

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datasheet Download

Link URL