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AK4641 Datasheet(PDF) 10 Page - Asahi Kasei Microsystems |
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AK4641 Datasheet(HTML) 10 Page - Asahi Kasei Microsystems |
10 / 51 page ASAHI KASEI [AK4641] MS0301-E-00 2004/05 - 10 - DC CHARACTERISTICS (Ta= −10 ∼ 70°C; AVDD, DVDD, BVDD=2.6 ∼ 3.6V) Parameter Symbol min typ Max Units High-Level Input Voltage VIH 70%DVDD - - V Low-Level Input Voltage VIL - - 30%DVDD V Input Voltage at AC Coupling (Note 18) VAC 50%DVDD - - V High-Level Output Voltage (Iout= −200µA) VOH DVDD −0.2 - - V Low-Level Output Voltage (Except SDA pin: Iout=200 µA) VOL - - 0.2 V (SDA pin: Iout=3mA) VOL - - 0.4 V Input Leakage Current Iin - - ±10 µA Note 18. The external clock is input to MCLK pin via AC coupled capacitor. SWITCHING CHARACTERISTICS (Ta= −10 ∼ 70°C; AVDD, DVDD, BVDD=2.6 ∼ 3.6V; C L=20pF) Parameter Symbol min typ max Units 16bit Stereo CODEC Interface Timing: Master Clock Timing (MCLK pin) Frequency fCLK 1.792 - 12.288 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns AC Pulse Width (Note 19) tACW 0.4/fCLK - - ns LRCK Timing Frequency fs 7 - 48 kHz Duty Cycle Duty 45 - 55 % Audio Interface Timing BICK Period tBCK 312.5 - - ns BICK Pulse Width Low tBCKL 130 - - ns Pulse Width High tBCKH 130 - - ns LRCK Edge to BICK “ ↑” (Note 20) tLRB 50 - - ns BICK “ ↑” to LRCK Edge (Note 20) tBLR 50 - - ns LRCK to SDTO (MSB) (Except I 2S mode) tLRS - - 80 ns BICK “ ↓” to SDTO tBSD - - 80 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Note 19. Refer to Figure 3. Note 20. BICK rising edge must not occur at the same time as LRCK edge. |
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