W567CXXX

- 11 -

(c) Crystal

(2)

(1)

VDD/ VDDOSC

VDD_BP1/

VSS

VSSSPK

/ RESET

PWM+/DAC

BP00

|

BP07

BP10

|

BP17

Speaker0

VDDSPK

0.1uF

PWM-

(3)

0 .1uF

4.7uF

Reset

Switch

CVDD

Speaker 0

8050

VDDSPK

Rs

(5)

10ohm

BP20

|

VDD1

BP27

PWM1+/DAC

Speaker1

PWM1-

Speaker 1

8050

VDDSPK

Rs

(5)

(4)

(4)

OSCIN

OSCOUT

X32I

Cp 1

Cp 2

Cp3

Cp4

X32O

Notes:

1.

The block (1): Please refer to (a) and (b) circuits for two-battery or three-battery application.

2.

The block (2): The low-pass filter circuit is necessary for VDD stability, in order to avoid VDDSPK noise.

3.

The block (3): The capacitor, 4.7uF, shunted between VDD and GND is necessary for power stability. However the

value of capacitor depends on the power loading of the application

4.

The block (4): Cp1 and Cp2 (15~30pF) are optional for main Crystal, which can be skipped normally.

5.

The block (5): The Rs value is suggested of 270

 ~ 1K to limit large DAC output current flowing into transistor.

6.

Cp3 and Cp4 (15~30pF) are optional for 32KHz Crystal, which can be skipped normally.

7.

Please connect all VDD pins include VDDOSC/VDD_BP1 to VDD. If with SIM application, the VDD_BP1 pin can

connect to different voltage for SPI flash or W551Cxx and the BP10~BP17 also use the same power VDD_BP1.

8.

The above application circuit is for reference only. No warranty for mass production.

9.

Other application circuits please refer to Design Guide.