BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /

Memory ICs

BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W

5/12

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Operating timing characteristics

BR9080AF-W / ARFV-W / ARFVM-W, BR9016AF-W / ARFV-W / ARFVM-W

(Unless otherwise noted, Ta=

Parameter

Symbol

Min.

Typ.

Max.

Unit

100

−−

ns

100

−−

ns

100

−−

ns

100

−−

ns

−−

150

ns

−−

150

ns

−−

10

ms

250

−−

ns

−−

150

ns

0

−

150

ns

230

−−

ns

230

−−

ns

0

−−

ns

0

−−

ns

CS setup time

Time when DO goes HIGH-Z (via CS)

Data clock high level time

Write control hold time

Data setup time

Data hold time

DO rise delay time

DO fall delay time

Self-timing programming cycle

CS minimum high level time

READY / BUSY display valid time

CS hold time

Data clock low level time

Write control setup time

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Timing chart

Synchronous Data Input Output Timing

CS

SK

DI

DO

WC

· Input data are clocked in to DI at the rising edge of the clock (SK).

· Output data will toggle on the falling edge of the SK clock.

· The WC pin does not have any effect on the READ, EWEN and EWDS operations.

Fig.2