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5962-89570 Datasheet(PDF) 8 Page - Broadcom Corporation. |
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5962-89570 Datasheet(HTML) 8 Page - Broadcom Corporation. |
8 / 16 page Broadcom - 8 - HCPL-540x, 5962-89570, HCPL-543x, HCPL-643x, 5962-89571 Data Sheet Electrical Characteristics Electrical Characteristics TA = –55°C to +125°C, 4.75V ≤ VCC ≤ 5.25V, 6 mA ≤ IF(ON) ≤ 10 mA, 0V ≤ VF(OFF) ≤ 0.7V, unless otherwise specified. Parameter Sym Test Conditions Group A Subgroupsa a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and Class K parts receive 100% testing at 25°C, 125°C, and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). Limits Unit Fig Notes Min Typb b. All typical values are at VCC = 5V, TA = 25°C, IF = 8 mA unless otherwise specified. Max Low Level Output Voltage VOL IOL = 8.0 mA (5 TTL Loads) 1, 2, 3 — 0.3 0.5 V 1 c c. Each channel. High Level Output Voltage VOH IOH = –4.0 mA 1, 2, 3 2.4 — — V 2 c Output Leakage Current IOHH VO = 5.25V, VF = 0.7V 1, 2, 3 — — 100 μA c Logic High Supply Current Single Channel ICCH VCC = 5.25V, VE = 0V 1, 2, 3 — 17 26 mA Dual Channel — 34 52 d d. The HCPL-6430, HCPL-6431, and HCPL-643K dual-channel parts function as two independent single-channel units. Use the single-channel parameter limits. Logic Low Supply Current Single Channel ICCL 1, 2, 3 — 19 26 mA Dual Channel — 38 52 d Input Forward Voltage VF IF = 10 mA 1, 2, 3 1.0 1.35 1.85 V 4 c Input Reverse Breakdown Voltage VR IR = 10 μA 1, 2, 3 3.0 4.8 — V c Input-Output Insulation Leakage Current II-O VI-O = 1500 Vdc, RH ≤ 65%, t = 5s 1— — 1.0 μA e, f e. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads or terminals shorted together. f. This is a momentary withstand test, not an operating condition. Propagation Delay Time Logic Low Output tPHL 9, 10, 11 — 33 60 ns 5, 6, 7 g, c g. tPHL propagation delay is measured from the 50% point on the rising edge of the input current pulse to the 1.5V point on the falling edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the falling edge of the input current pulse to the 1.5V point on the rising edge of the output pulse. Pulse Width Distortion, PWD = |tPHL – tPLH|. Propagation Delay Time Logic High Output tPLH 9, 10, 11 — 30 60 ns 5, 6, 7 g, c Pulse Width Distortion PWD 9, 10, 11 — 3 35 ns 5, 6, 7 g, c Logic High Common-Mode Transient Immunity |CMH|VCM = 50 VP-P, IF = 0 mA 9, 10, 11 500 3000 — V/μs 11 h, c, i h. CML is the maximum slew rate of the common-mode voltage that can be sustained with the output voltage in the logic low state (VO(MAX) < 0.8V). CMH is the maximum slew rate of the common-mode voltage that can be sustained with the output voltage in the logic high state (VO(MIN) > 2.0V). i. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots not specifically tested. Logic Low Common-Mode Transient Immunity |CML|VCM = 50 VP-P, IF = 6 mA 9, 10, 11 500 3000 — V/μs 11 h, c, i |
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