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TLV62569, TLV62569P

SLVSDG1B – DECEMBER 2016 – REVISED JUNE 2017

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Copyright © 2016–2017, Texas Instruments Incorporated

Feature Description (continued)

7.3.3 Soft Startup

After enabling the device, internal soft startup circuitry ramps up the output voltage which reaches nominal output

voltage during a startup time. This avoids excessive inrush current and creates a smooth output voltage rise

slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal

impedance.

The TLV62569 is able to start into a pre-biased output capacitor. The converter starts with the applied bias

voltage and ramps the output voltage to its nominal value.

7.3.4 Switch Current Limit

The switch current limit prevents the device from high inductor current and drawing excessive current from a

battery or input voltage rail. Excessive current might occur with a heavy load or shorted output circuit condition.

The TLV62569 adopts the peak current control by sensing the current of the high-side switch. Once the high-side

switch current limit is reached, the high-side switch is turned off and low-side switch is turned on to ramp down

the inductor current with an adaptive off-time.

7.3.5 Under Voltage Lockout

To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down

7.3.6 Thermal Shutdown

The device enters thermal shutdown once the junction temperature exceeds the thermal shutdown rising

operation automatically.

7.4 Device Functional Modes

7.4.1 Enabling/Disabling the Device

The device is enabled by setting the EN input to a logic High. Accordingly, a logic Low disables the device. If the

device is enabled, the internal power stage starts switching and regulates the output voltage to the set point

voltage. The EN input must be terminated and should not be left floating.

7.4.2 Power Good

The TLV62569P has a power good output. The PG pin goes high impedance once the output is above 95% of

the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.

The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up

resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails

by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used.

Table 1. PG Pin Logic

DEVICE CONDITIONS

LOGIC STATUS

HIGH Z

LOW

Enable

√

√

Shutdown

EN = Low

√

Thermal Shutdown

√

UVLO

√

Power Supply Removal

√