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GS71116AU-12 Datasheet(PDF) 2 Page - GSI Technology |
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GS71116AU-12 Datasheet(HTML) 2 Page - GSI Technology |
2 / 14 page Memory Array Row Decoder Column Decoder Address Input Buffer Control I/O Buffer A0 CE WE OE DQ1 A15 DQ16 UB _____ GS71116AGP/U Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.10 1/2013 2/13 © 2001, GSI Technology Block Diagram Truth Table CE OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 VDD Current H X X X X Not Selected Not Selected ISB1, ISB2 L L H L L Read Read IDD L H Read High Z H L High Z Read L X L L L Write Write L H Write Not Write, High Z H L Not Write, High Z Write L H H X X High Z High Z L X X H H High Z High Z Note: X: “H” or “L” |
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