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ADS114S08BIPBS Datasheet(PDF) 8 Page - Texas Instruments |
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ADS114S08BIPBS Datasheet(HTML) 8 Page - Texas Instruments |
8 / 88 page 8 ADS114S06B, ADS114S08B SBAS852 – AUGUST 2017 www.ti.com Product Folder Links: ADS114S06B ADS114S08B Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal oscillator, and all data rates (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (3) The IDAC current does not change by more than 0.1% from the nominal value when staying within the specified compliance voltage. VOLTAGE REFERENCE INPUTS Absolute input current Reference buffers disabled, external VREF = 2.5 V, REFP1/REFN1 inputs 4 µA/V Reference buffers enabled, external VREF = 2.5 V, REFP1/REFN1 inputs 5 nA INTERNAL VOLTAGE REFERENCE VREF Output voltage 2.5 V Accuracy TA = 25°C –0.2% ±0.01% 0.2% Temperature drift 8 40 ppm/°C Output current AVDD = 2.7 V to 3.3 V, sink and source –5 5 mA AVDD = 3.3 V to 5.25 V, sink and source –10 10 Short-circuit current limit Sink and source 70 100 mA PSRR Power-supply rejection ratio AVDD at dc 85 dB Load regulation AVDD = 2.7 V to 3.3 V, load current = –5 mA to 5 mA 8 µV/mA AVDD = 3.3 V to 5.25 V, load current = –10 mA to 10 mA 8 Startup time 1-µF capacitor on REFOUT, 0.001% settling 5.9 ms Capacitive load stability Capacitor on REFOUT 1 47 µF Reference noise f = 0.1 Hz to 10 Hz, 1-µF capacitor on REFOUT 9 µVPP INTERNAL OSCILLATOR fCLK Frequency 4.096 MHz Accuracy –2% 2% EXCITATION CURRENT SOURCES (IDACS) Current settings 10, 50, 100, 250, 500, 750, 1000, 1500, 2000 µA Compliance voltage(3) 10 µA to 750 µA, 0.1% deviation AVSS AVDD – 0.4 V 1 mA to 2 mA, 0.1% deviation AVSS AVDD – 0.6 Accuracy (each IDAC) TA = 25°C, 10 µA to 2 mA –6% ±1% 6% Current mismatch between IDACs TA = 25°C, 10 µA to 2 mA 0.2% Temperature drift (each IDAC) 10 µA to 2 mA 100 ppm/°C Temperature drift matching between IDACs 10 µA to 2 mA 10 ppm/°C Startup time With internal reference already settled. From end of WREG command to current flowing out of pin. 22 µs BIAS VOLTAGE VBIAS Output voltage (AVDD + AVSS) / 2 V Output impedance 350 Ω Startup time Combined capacitive load on all selected analog inputs CLOAD = 1 µF, 0.1% settling 2.8 ms BURNOUT CURRENT SOURCES (BOCS) Current settings 0.2, 1, 10 µA Accuracy 0.2 µA, sinking or sourcing ±8% 1 µA, sinking or sourcing ±4% 10 µA, sinking or sourcing ±2% SUPPLY VOLTAGE MONITORS Accuracy (AVDD – AVSS) / 4 monitor ±1% DVDD / 4 monitor ±1% |
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