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TPS650932ZAJR Datasheet(PDF) 8 Page - Texas Instruments |
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TPS650932ZAJR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 121 page  8 TPS650932 SLVSE36 – AUGUST 2017 www.ti.com Submit Documentation Feedback Pin Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Pin Attributes—ZAJ Package (continued) PIN I/O TYPE(1) DESCRIPTION NO. NAME G2 BAT2SWON O D Battery 2 switch-on power path. This pin is an open-drain output and is active low. G3 VDCSNS I AS VDC voltage monitor G4 FBVR5P I AS VR5 positive-feedback remote sense. Connect this pin to the output voltage of VR5 at the output-load capacitor. G5 AGND — A Analog ground. Tie this pin directly to the ground plane. G6 AGND — A Analog ground. Tie this pin directly to the ground plane. G7 AGND — A Analog ground. Tie this pin directly to the ground plane. G8 AGND — A Analog ground. Tie this pin directly to the ground plane. G9 VINVR3 I AS VR3 input-voltage sense and high-side current-sense. Kelvin connect this pin to the drain of high-side FET. G10 FBVR2P I AS VR2 positive-feedback remote sense. Connect this pin to the output voltage of VR2 at the output-load capacitor. G11 ALL_SYS_PWRGD O D Non-core rails power-good pin. Power-good pin for all PMIC and specified monitored VRs. This pin is an open-drain output. G12 PGNDVR2 — VR VR2 power ground G13 PGNDVR2 — VR VR2 power ground H1 SDA I/O D I2C data H2 PWRBTNIN I AS Power-button input (internal pullup to LDO3V). This pin is active low. H3 VCCIO_ENOUT O D Qualified enable for VCCIO rail. H4 V5ADS3_ENOUT O D Power-good comparator F output for V18S or V33A_PCH and enable to the PoL load switch or regulator (push-pull to VDDPG) H5 AGND — A Analog ground. Tie this pin directly to the ground plane. H6 AGND — A Analog ground. Tie this pin directly to the ground plane. H7 AGND — A Analog ground. Tie this pin directly to the ground plane. H8 AGND — A Analog ground. Tie this pin directly to the ground plane. H9 NVDC I D NVDC select. This pin has two levels: low = NVDC, high = non-NVDC. Connect the NVDC pin to ground for NVDC. Connect the NVDC pin to the LDO3V pin for non- NVDC. H10 TRIP O D VCOMP comparator push-pull output. This pin is active low. H11 SYS_PWROK O D Delayed version of the ALL_SYS_PWRGD pin. This pin is an open-drain output. H12 SWVR2 I VR VR2 switch-node connection H13 SWVR2 I VR VR2 switch-node connection J1 SCLK I D I2C clock J2 ACSWON O D AC adaptor switch-on power path. This pin is an open-drain output and is active low. J3 EC_RST O D EC reset. This pin is an open-drain output and is active low. J4 VCOMP I AS VCOMP comparator input J5 AGND — A Analog ground. Tie this pin directly to the ground plane. J6 AGND — A Analog ground. Tie this pin directly to the ground plane. J7 AGND — A Analog ground. Tie this pin directly to the ground plane. J8 AGND — A Analog ground. Tie this pin directly to the ground plane. J9 FBVR1N I AS VR1 negative-feedback remote sense. Connect this pin to the GND of the VR1 pin at the output-load capacitor. J10 V105S I AS Power-good comparator G input and discharge path for the V105S rail J11 RSMRST_PWRGD O D Resume-reset power good. This pin is an open-drain output and is active low. J12 SLP_S3 I D Input for SLP_SUS signal for the power-good tree J13 VCCIO_ENIN I D Enable for power good comparator D which is V33A_DSW K1 AGND2 — A Analog ground 2. Tie this pin directly to the ground plane. K2 PCH_PWRBTN O D Power-button signal to PCH. This pin is an open-drain output and is active low. K3 EN3V3SW I D Enable for load switch from the LDO3V pin to the VOUT3V3SW output pin |
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