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TMS320F280041C Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320F280041C Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 217 page  8 TMS320F280049, TMS320F280049C, TMS320F280049M TMS320F280048, TMS320F280048C, TMS320F280045 TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C SPRS945A – JANUARY 2017 – REVISED AUGUST 2017 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280049M TMS320F280048 TMS320F280048C TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C Revision History Copyright © 2017, Texas Instruments Incorporated • Table 5-31 (cJTAG Timing Requirements): Updated table. ................................................................... 84 • Table 5-32 (cJTAG Switching Characteristics): Updated table. .............................................................. 84 • Section 5.8.6.1 (GPIO – Output Timing): Changed "GPO" to "GPIO". ...................................................... 85 • Table 5-33 (General-Purpose Output Switching Characteristics), Toggling frequency: Changed "tfGPO" to "fGPIO". ... 85 • Table 5-43 (HALT Mode Switching Characteristics): Changed "CPU1" to "CPU". ........................................ 94 • Section 5.9 (Analog Peripherals): Updated list of analog subsystem features. ............................................ 96 • Figure 5-29 (Analog Subsystem Block Diagram (64-Pin PM LQFP)): Added footnote. ................................... 98 • Figure 5-30 (Analog Subsystem Block Diagram (56-Pin RSH VQFN)): Added footnote. ................................. 99 • Figure 5-31 (Analog Group Connections): Updated figure. ................................................................. 100 • Section 5.9.1 (Analog-to-Digital Converter (ADC)): Updated list of ADC features. ...................................... 104 • Figure 5-32 (ADC Module Block Diagram): Updated figure. ................................................................ 105 • Table 5-47 (ADC Operating Conditions): Updated table. .................................................................... 107 • Table 5-48 (ADC Characteristics): Updated table. ............................................................................ 107 • Table 5-50 (Per-Channel Parasitic Capacitance): Updated table. .......................................................... 111 • Section 5.9.2 (Programmable Gain Amplifier (PGA)): Updated list of PGA features. ................................... 114 • Table 5-52 (PGA Characteristics): Updated table. ........................................................................... 115 • Table 5-53 (Temperature Sensor Characteristics): Updated table. ........................................................ 117 • Section 5.9.4 (Buffered Digital-to-Analog Converter (DAC)): Updated section. .......................................... 118 • Figure 5-36 (DAC Module Block Diagram): Updated figure. ................................................................ 118 • Table 5-54 (Buffered DAC Electrical Characteristics): Updated table. ..................................................... 119 • Section 5.9.5 (Comparator Subsystem (CMPSS)): Added NOTE about CMPSS pins. ................................. 122 • Section 5.9.5: Removed "CMPSS Connectivity (64-Pin PM)" figure. ...................................................... 122 • Section 5.9.5: Removed "CMPSS Connectivity (56-Pin RSH)" figure. ..................................................... 122 • Figure 5-40 (CMPSS Connectivity): Changed figure title from "CMPSS Connectivity (100-Pin PZ)" to "CMPSS Connectivity". ....................................................................................................................... 122 • Table 5-55 (Comparator Electrical Characteristics): Updated table. ........................................................ 123 • Table 5-56 (CMPSS DAC Static Electrical Characteristics): Updated table. .............................................. 123 • Section 5.10.1 (Enhanced Capture (eCAP)): Updated section. ............................................................ 127 • Figure 5-46 (eCAP Block Diagram): Updated figure and added footnote. ................................................ 128 • Table 5-57 (eCAP Timing Requirements): Updated table. .................................................................. 129 • Table 5-58 (eCAP Switching Charcteristics): Updated table. ............................................................... 129 • Section 5.10.2 (High-Resolution Capture Submodule (HRCAP6–HRCAP7)): Updated section. ....................... 130 • Figure 5-47 (HRCAP Block Diagram): Updated figure and added footnote. .............................................. 131 • Section 5.10.2.1 (HRCAP Electrical Data and Timing): Updated section. ................................................. 132 • Table 5-59 (HRCAP Switching Characteristics): Updated table. ........................................................... 132 • Figure 5-48 (HRCAP Accuracy Precision and Resolution): Added figure. ................................................ 132 • Figure 5-49 (HRCAP Standard Deviation Characteristics): Updated figure and footnotes. ............................. 133 • Figure 5-50 (ePWM Submodules and Critical Internal Signal Interconnects): Updated figure. ......................... 135 • Figure 5-51 (ePWM Trip Input Connectivity): Updated figure. .............................................................. 136 • Table 5-60 (ePWM Timing Requirements): Updated table. ................................................................. 138 • Table 5-61 (ePWM Switching Characteristics): Updated table. ............................................................. 138 • Section 5.10.5 (Enhanced Quadrature Encoder Pulse (eQEP)): Updated section. ...................................... 141 • Table 5-65 (eQEP Timing Requirements): Updated table. .................................................................. 142 • Table 5-66 (eQEP Switching Characteristics): Updated table. .............................................................. 142 • Section 5.10.6 (Sigma-Delta Filter Module (SDFM)): Updated list of SDFM features. .................................. 143 • Figure 5-56 (SDFM Block Diagram): Updated figure. ........................................................................ 144 • Table 5-67 (SDFM Timing Requirements): Updated table. .................................................................. 145 • Section 5.11.1 (Controller Area Network (CAN)): Changed "D_CAN" to "DCAN". ....................................... 147 • Figure 5-61 (CAN Block Diagram): Updated figure. .......................................................................... 148 • Section 5.11.2 (Inter-Integrated Circuit (I2C)): Updated list of I2C module features. .................................... 149 • Table 5-68 (I2C Timing Requirements): Updated table. ...................................................................... 151 • Table 5-69 (I2C Switching Characteristics): Updated table. ................................................................. 151 • Section 5.11.3 (Power Management Bus (PMBus) Interface): Added "Support for I2C mode" feature. .............. 152 • Section 5.11.3: Updated "Fast Mode+: 1000 kHz" feature. ................................................................. 152 • Table 5-70 (PMBus Electrical Characteristics): Updated table. ............................................................. 153 • Table 5-71 (PMBus Fast Mode Switching Characteristics): Updated table. .............................................. 153 • Table 5-72 (PMBus Standard Mode Switching Characteristics): Updated table. ......................................... 153 • Section 5.11.5.1 (SPI Electrical Data and Timing): Updated section. ...................................................... 159 • Figure 5-67 (SPI Master Mode External Timing (Clock Phase = 1)): Updated figure. ................................... 162 • Figure 5-69 (SPI Slave Mode External Timing (Clock Phase = 1)): Updated figure. .................................... 164 |
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