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SN74LV163ADR Datasheet(PDF) 5 Page - Texas Instruments |
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SN74LV163ADR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 20 page SN54LV163A, SN74LV163A 4BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (synchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit Data Inputs Data Outputs CLR LOAD A B C D CLK ENP ENT RCO QA QB QC QD Async Clear Sync Clear Preset Count Inhibit 12 13 14 15 0 1 2 |
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