GS8673ED18/36BK-725S/625S/550S

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.04 6/2015

6/25

© 2012, GSI Technology

Power-Up and Reset Requirements

For reliability purposes, power supplies must power up simultaneously, or in the following sequence:

Power supplies must power down simultaneously, or in the reverse sequence.

After power supplies power up, the following start-up sequence must be followed.

Step 1 (Recommended, but not required): Assert RST High for at least 1ms.

While RST is asserted high:

• Read and Write operations are ignored.

Note: If possible, RST should be asserted High before input clocks (begin toggling, and remain asserted High until input clocks are

stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM.

Step 2: Begin toggling input clocks.

After input clocks begin toggling, but not necessarily within specification:

• CQ, CQ begin toggling, but not necessarily within specification.

Step 3: Wait until input clocks are stable and toggling within specification.

Step 4: De-assert RST Low (if asserted High).

Step 5: Wait at least 160K (163,840) cycles for driver and ODT impedances to calibrate.

After the impedances have calibrated:

• CQ, CQ begin toggling within specification.

Step 6: Begin initiating Read and Write operations.

Reset Usage

Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence

described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted

Low (as in Step 4 in the power up sequence), at least 160K NOP cycles must be initiated (as in Step 5 in the power-up sequence)

before Read and Write operations are initiated.

Note: Memory array content may be perturbed/corrupted when RST is asserted High.