GS8673EQ18/36BK-675/625/550/500

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.06 5/2012

6/31

© 2011, GSI Technology

Power Up Requirements

For reliability purposes, power supplies must power up simultaneously, or in the following sequence:

Power supplies must power down simultaneously, or in the reverse sequence.

After power supplies power up, the following start-up sequence must be followed.

Step 1 (Recommended, but not required): Assert RST High for at least 1ms.

While RST is asserted high:

• The DLL is disabled, regardless of the state of the DLL pin.

• Read and Write operations are ignored.

Note: If possible, RST should be asserted High before input clocks (CK, CK, KD, KD) begin toggling, and remain asserted High

until input clocks are stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing

trouble in the SRAM.

Step 2: Begin toggling input clocks.

After input clocks begin toggling, but not necessarily within specification:

• Q are placed in the non-Read state, and remain so until the first Read operation.

• QVLD are driven Low, and remain so until the first Read operation.

• CQ, CQ begin toggling, but not necessarily within specification.

Step 3: Wait until input clocks are stable and toggling within specification.

Step 4: De-assert RST Low (if asserted High).

Step 5: Wait at least 160K (163,840) cycles.

During this time:

• Output driver and input termination impedances are calibrated (i.e. set to the programmed values).

Note: The DLL pin may be asserted High or de-asserted Low during this time. If asserted High, DLL synchronization begins

immediately after output driver and input termination impedance calibration has completed. If de-asserted Low, DLL

synchronization begins after the DLL pin is asserted High (see Step 6). In either case, Step 7 must follow thereafter.

Step 6: Assert DLL pin High (if de-asserted Low).

Step 7: Wait at least 64K (65,536) cycles.

During this time:

• The DLL is enabled and synchronized properly.

After DLL synchronization has completed:

• CQ, CQ begin toggling within specification.

Step 8: Begin initiating Read and Write operations.