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GS8673EQ18BK-625I Datasheet(PDF) 9 Page - GSI Technology |
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GS8673EQ18BK-625I Datasheet(HTML) 9 Page - GSI Technology |
9 / 31 page GS8673EQ18/36BK-675/625/550/500 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.06 5/2012 9/31 © 2011, GSI Technology Functional Description Separate I/O ECCRAMs, from a system architecture point of view, are attractive in applications that execute continuous back-to-back alternating Reads and Writes. Therefore, the SigmaQuad-IIIe ECCRAM interface and truth table are optimized for continuously alternating Reads and Writes. Separate I/O ECCRAMs are unpopular in applications where block transfers of Reads or Writes are needed because half of the data pins will go unused during the block transfer, potentially cutting Separate I/O ECCRAM data bandwidth in half. Applications of this sort are better served by Common I/O ECCRAMs such as the SigmaDDR-IIIe series. Truth Table SA R W Current Operation D Q ↑CK (tn) ↑CK (tn+½) ↑CK (tn) ↑CK (tn) (tn) ↑KD (tn) ↑KD (tn+½) ↑CK (tm) ↑CK (tm+½) X X 1 1 NOP X X Hi-Z / 0 Hi-Z / 0 X V 1 0 Write Only D1 D2 Hi-Z / 0 Hi-Z / 0 V X 0 1 Read Only X X Q1 Q2 V V 0 0 Read + Write D1 D2 Q1 Q2 Notes: 1. 1 = input High; 0 = input Low; V equals input valid; X = input don’t care. 2. tm = tn + RL, where RL = Read Latency of the device. 3. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations. 4. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations. 5. When D input termination is disabled (MZT[1:0] = 00), Q drivers are disabled (i.e. Q pins are tri-stated) for one cycle in response to NOP and Write commands, RL cycles after the command is sampled. 6. When D input termination is enabled (MZT[1:0] = 01 or 10), Q drivers are enabled Low (i.e. Q pins are driven Low) for one cycle in response to NOP and Write Only commands, RL cycles after the command is sampled. This is done so the Memory Controller can enable On-Die Termination on its data inputs without having to cope with the termination pulling tri-stated data inputs to VDDQ/2 (i.e. to the switch point of the data input receivers). |
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