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X9252TV24I-2.7 Datasheet(PDF) 6 Page - Xicor Inc. |
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X9252TV24I-2.7 Datasheet(HTML) 6 Page - Xicor Inc. |
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6 / 21 page  6 of 21 REV 1.4.1 7/29/03 www.xicor.com X9252 2-WIRE INTERFACE TIMING(S) SDA vs. SCL Timing WP, A0, A1, and A2 Pin Timing Symbol Parameter Min. Max. Units fSCL Clock Frequency 400 kHz tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Condition Setup Time 600 ns tHD:STA Start Condition Hold Time 600 ns tSU:STO Stop Condition Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR (5) SCL and SDA Rise Time 300 ns tF (5) SCL and SDA Fall Time 300 ns tAA (5) SCL Low to SDA Data Output Valid Time 0.9 µs tDH SDA Data Output Hold Time 0 ns tIN (5) Pulse Width Suppression Time at SCL and SDA inputs 50 ns tBUF (5) Bus Free Time (Prior to Any Transmission) 1200 ns tSU:WPA (5) A0, A1, A2 and WP Setup Time 600 ns tHD:WPA (5) A0, A1, A2 and WP Hold Time 600 ns tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DAT SCL SDA (Input Timing) SDA (Output Timing) tF tLOW tBUF tAA tR tHD:WP SCL SDA IN WP, A0, A1, or A2 tSU:WP Clk 1 START STOP |
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