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X9279UBI-2.7 Datasheet(PDF) 5 Page - Xicor Inc. |
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X9279UBI-2.7 Datasheet(HTML) 5 Page - Xicor Inc. |
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5 / 24 page  X9279 Characteristics subject to change without notice. 5 of 24 REV 1.1.7 2/6/03 www.xicor.com PRINCIPLES OF OPERATION The X9279 is a integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following: – Resistor Array Description. – Serial Interface Description. – Instruction and Register Description. Array Description The X9279 is comprised of a resistor array (see Figure 1). The array contains, in effect, 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (see Table 1). The WCR may be written directly. These Data Registers can the WCR can be read and written by the host system. Power Up and Down Recommendations. There are no restrictions on the power-up or power- down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate specification is always in effect. Figure 1. Detailed Potentiometer Block Diagram SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 SERIAL BUS INPUT PARALLEL BUS INPUT COUNTER REGISTER INC/DEC LOGIC UP/DN CLK MODIFIED SCK UP/DN RH RL RW 8 8 C O U N T E R D E C O D E IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH WIPER (WCR) BANK_0 Only (DR0) (DR1) (DR2) (DR3) |
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