1

Rev. I

04/16/03

IS41C16100

IS41LV16100

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice.

ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

• TTL compatible inputs and outputs; tristate I/O

• Refresh Interval:

— Auto refresh Mode: 1,024 cycles /16 ms

—

RAS-Only, CAS-before-RAS (CBR), and Hidden

— Self refresh Mode - 1,024 cycles / 128ms

• JEDEC standard pinout

• Single power supply:

— 5V ± 10% (IS41C16100)

— 3.3V ± 10% (IS41LV16100)

• Byte Write and Byte Read operation via two

CAS

DESCRIPTION

The

high-performance CMOS Dynamic Random Access Memories.

These devices offer an accelerated cycle access called EDO Page

Mode. EDO Page Mode allows 1,024 random accesses within a

single row with access cycle time as short as 20 ns per 16-bit word.

The Byte Write control, of upper and lower byte, makes the

IS41C16100idealforusein16-bitand32-bitwidedatabussystems.

ThesefeaturesmaketheIS41C16100andIS41LV16100ideallysuited

for high-bandwidth graphics, digital signal processing, high-

performance computing systems, and peripheral applications.

The IS41C16100 and IS41LV16100 are packaged in a 42-pin 400-

milSOJand400-mil50-(44-)pinTSOP(TypeII).Thelead-free400-

mil 50- (44-) option is available too.

1M x 16 (16-MBIT) DYNAMIC RAM

WITH EDO PAGE MODE

KEY TIMING PARAMETERS

Parameter

-50

-60

Unit

Max.

5060ns

Max.

1315ns

2530ns

2025ns

84

104

ns

PIN CONFIGURATIONS

50(44)-Pin TSOP (Type II)

42-Pin SOJ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

NC

NC

WE

RAS

NC

NC

A0

A1

A2

A3

VCC

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

NC

LCAS

UCAS

OE

A9

A8

A7

A6

A5

A4

GND

PIN DESCRIPTIONS

A0-A9

Address Inputs

I/O0-15

Data Inputs/Outputs

WE

Write Enable

OE

Output Enable

RAS

Row Address Strobe

UCAS

Upper Column Address Strobe

LCAS

Lower Column Address Strobe

Vcc

Power

GND

Ground

NC

No Connection

April 2003

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

NC

NC

NC

WE

RAS

NC

NC

A0

A1

A2

A3

VCC

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

NC

NC

LCAS

UCAS

OE

A9

A8

A7

A6

A5

A4

GND