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Z53C80SCSI Datasheet(PDF) 1 Page - Zilog, Inc. |
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Z53C80SCSI Datasheet(HTML) 1 Page - Zilog, Inc. |
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1 / 40 page  1 Z53C80 SCSI ZILOG PS97SCC0200 FEATURES PRODUCT SPECIFICATION Z53C80 SMALL COMPUTER SYSTEM INTERFACE (SCSI) s Asynchronous Interface (Supports 3 MB/s) s Direct SCSI Bus Interface with On-Board 48 mA Drivers s Supports Target and Initiator Roles s Meets SCSI Protocol as Defined in ANSI X3.131-1986 Standard s Added “Glitch Eater” Enhancement to Minimize Bus Reflection ® Apple Macintosh is a registered trademark of Apple Computer, Inc. s Pin Compatible with the Industry Standard 5380 s 44-Pin PLCC or 48-Pin DIP Package Styles s DMA or Programmed I/O Data Transfers s Arbitration Support s Supports Normal or Block Mode DMA s Memory or I/O Mapped CPU Interface GENERAL DESCRIPTION The Z53C80 SCSI (Small Computer System Interface) controller is designed to implement the SCSI protocol as defined by the ANSI X3.131-1986 standard, and it is fully compatible with the industry standard 5380. The device is capable of operating both as a Target and as an Initiator. Special high-current open-drain outputs enable it to directly interface to the SCSI bus. The Z53C80 has the necessary interface hook-ups which allow the system CPU to communicate with it as with any other peripheral device. The CPU can read from, or write to, the SCSI registers which are addressed as standard or memory-mapped I/Os. The Z53C80 increases the system performance by minimizing the CPU intervention in DMA operations which the SCSI controls. The CPU is interrupted by the SCSI when it detects a bus condition that requires attention. It also supports arbitration and reselection. The Z53C80 has the proper handshake signals to support normal and block mode DMA operations with most DMA controllers available. The added enhancement known as the “Glitch Eater” is used to minimize effects of bus reflection on improperly terminated SCSI bus applications. The high frequency reflections that can occur on the SCSI bus are filtered out, reducing the sensitivity of the inputs, specifically /REQ and /ACK to bus signal reflections. Figure 1 shows a worst case input waveform (labeled A), along with the filtered input (labeled B) and the output of a Schmitt trigger used to provide the hysteresis required on SCSI inputs (labeled C). This enhancement is a requirement for the device to function properly in a Apple Macintosh® environment. Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power V CC V DD Ground GND V SS |
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