© IMP, Inc.

IMP8980D DS-5-00

4

Figure5 - Connection Memory High Bits

76

54

32

10

No Corresponding Memory

- These bits give 0s if read.

Per Channel

Control Bits

BIT

NAME

DESCRIPTION

2

Message

When 1, the contents of the corresponding location in Connection

Channel

Memory Low are output on the location’s channel and stream.

When 0, the contents of the corresponding location in Connection

Memory Low act as an address for the Data Memory and so

determine the source of the connection to the location’s channel

and stream.

1

CSTo

This bit is output on the CSTo pin one channel early. The CSTo bit

for stream 0 is output first.

0

Output

If the ODE pin is high and bit 6 of the Control Register is 0, then

Enable

this bit enables the output driver for the location’s channel and

stream. This allows individual channels on individual streams to

be made high-impedance, allowing switching matrices to be

constructed. A "1" enables the driver and a "0" disables it.

If the ODE pin is low, then all serial

outputs are high-impedance. If it is high

and bit 6 in the Control Register is 1, then

all outputs are active. If the ODE pin is

high and bit 6 in the Control Register is 0,

then the bit 0 in the Connection Memory

High location enables the output drivers

for the corresponding individual ST-BUS

output stream and channel. Bit 0=1

enables the driver and bit 0=0 disables it

(see Figure 5).

Bit 1 of each Connection Memory High

location (see Figure 5) is output on the

CSTo pin once every frame. To allow for

delay in any external control circuitry the

bit is output one channel before the

corresponding channel on the ST-BUS

streams, and the bit for stream 0 is output

first in the channel; e.g., bit 1’s for

channel 9 of streams 0-7 are output

synchronously with ST-BUS channel 8

bits 7-0.

Applications

Digital Switching Systems

Figures 7 and 8 show how IMP8980Ds

and MT8964s form a simple digital

switching system. Figure 7 shows the

interface between the IMP8980D’s and the

filter/codecs. Figure 8 shows the position of

these components in an example architec-

ture.

The Mitel MT8964 filter/codec in

Figure 7 receives and transmits digitized

voice signals on the ST-BUS input DR,

and ST-BUS output DX, respectively.

These signals are routed to the ST-BUS

inputs and outputs on the top IMP8980D,

which is used as a digital speech switch.

The MT8964 is controlled by the

ST-BUS input DC originating from the

bottom IMP8980D , which generates the

appropriate signals from an output channel

in Message Mode. This architecture

optimizes the messaging capability of the

line circuit by building signalling logic, e.g.,

for on-off hook detection, which commu-

nicates on an ST-BUS output. This

signalling ST-BUS output is monitored by

a microprocessor (not shown) through an

ST-BUS input on the bottom IMP8980D.

Figure 8 shows how a simple digital

switching system may be designed using the

ST-BUS architecture. This is a private

telephone network with 256 extensions

which uses a single IMP8980D as a speech