GS8672D19/37BE-450/400/375/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02c 8/2017

6/28

© 2011, GSI Technology

Power-Up Sequence for SigmaQuad-II+ ECCRAMs

SigmaQuad-II+ ECCRAMs must be powered-up in a specific sequence in order to avoid undefined operations.



1. After power supplies power-up and clocks (K, K) are stablized, 163,840 cycles are required to set Output Driver

Impedance.

2. Thereafter, an additional 65,536 clock cycles are required to lock the DLL after it has been enabled.

3. Begin Read and Write operations.

For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.

On-Chip Error Correction

SigmaQuad-II+ ECCRAMs implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on

each DDR data word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9],

D/Q[26:18], or D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible

to the user).

The ECC algorithm neither corrects nor detects multi-bit errors. However, GSI ECCRAMs are architected in such a way that a

single SER event very rarely causes a multi-bit error across any given "transmitted data unit", where a "transmitted data unit"

represents the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-

bit errors results in the SER mentioned previously (i.e., <0.002 FITs/Mb measured at sea level).

Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data

storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one "error bit" per eight "data bits", in any 9-bit

"data byte") for error detection (either simple parity error detection, or system-level ECC error detection and correction). Such

error-bit allocation is unnecessary with ECCRAMs —the entire memory array can be utilized for data storage, effectively

providing 12.5% greater storage capacity compared to SRAMs of the same density not equipped with on-chip ECC.