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ADN2849ACP-RL Datasheet(PDF) 2 Page - Analog Devices |
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ADN2849ACP-RL Datasheet(HTML) 2 Page - Analog Devices |
2 / 10 page ADN2849 Rev. Pr. G | Page 2 of 17 Specifications (Electrical Specifications (VEE=VEEMIN to VEEMAX . All specifications Tmin to Tmax, ZL=50Ω unless otherwise noted. Typical values specified at 250C) Table 1. Parameter Min Typ Max Unit Conditions Bias Offset Voltage(MODP) Bias offset voltage -0.25 -2.0 V Note 1 BIAS_SET voltage to bias offset voltage gain 0.9 1.1 V/V Ta=250C, VEE=-5.2V Bias offset voltage drift over temperature and VEE -5 5 % Modulation Voltage(MODP) Modulation voltage swing 0.6 3.0 V Note1 MOD_SET voltage to modulation voltage swing gain 1.5 1.9 V/v Ta=250C, VEE=-5.2V Modulation voltage drift over temperature and VEE -5 5 % Back termination resistance 40 60 Ω Rise time (20% - 80%) 27 36 ps Fall time (20% - 80%) 27 36 ps Random jitter 0.75 ps RMS Total jitter 10 psp-p Cross point adjust range 30 85 % Cross point drift over temperature and VEE -5 5 % Minimum output voltage(single ended) VEE+1.7 V Note1 |S22| -8 dB At 10GHz Modulation enable time 100 ns Modulation disable time 100 ns Data Inputs (DATAP, DATAN) Differential Input voltage 600 1600 mVp-p Termination resistance 40 60 Ω Setup time (see figure 2) 25 ps CLK_SELB=’0’ Hold time (see figure 2) 25 ps CLK_SELB=’0’ |S11| -10 DB At 10GHz Clock Inputs (CLKP, CLKN) Differential Input voltage 600 1600 mVp-p Termination resistance 40 60 Ω |S11| -10 dB At 10GHz Cross point adjust (CPAN, CPAP) Input voltage range -0.85 -1.85 V CPAP, CPAN differential voltage 0.6 Vp-p Input current 85 115 µA Logic Inputs (MOD_ENB, CLK_SELB) VIH VEE+2 V VIL VEE+0.8 V IIL -400 µA VI=VEE+0.4V IIH 20 µA VI=VEE+2.4V 200 µA VI=0V Supply VEE -4.75 -5.2 -5.5 V IMOD=0 IEE 52 mA VMODP/MODN=0 Notes: Minimum supply voltage and minimum output voltage determine maximum output swing and maximum bias offset that can be achieved concurrently. Measured using the characterization circuit shown in figure 3. Preliminary Technical Data |
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