7

FN7360.2

January 31, 2005

FIGURE 8. LOAD REGULATIONS

FIGURE 9. HTSSOP THERMAL RESISTANCE vs PCB AREA

(NO AIR FLOW)

FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE

610

590

585

01.5

2.5

4

595

0.5

2

3.5

600

605

1

3

0.8

-0.2

-0.4

04

0.6

0.2

12

3

0.4

0.0

50

45

40

35

30

25

123

456

789

CONDITION:

28-Pin HTSSOP THERMAL PAD

SOLDERED TO 2-LAYER PCB

WITH 0.039" THICKNESS AND

1 OZ. COPPER ON BOTH SIDES

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD HTSSOP EXPOSED

DIEPAD NOT SOLDERED TO PCB

1.2

1

0.8

0.4

0.2

0

0

25

50

75

100

150

AMBIENT TEMPERATURE (°C)

1.136W

125

85

0.6

θ

110

°C

/W

HT

SS

OP

28

4.5

4

3.5

2

1.5

0.5

0

0

25

50

75

100

150

AMBIENT TEMPERATURE (°C)

4.167W

125

85

2.5

1

3

θ

30°

C/W

HTS

SO

P2

8

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD HTSSOP EXPOSED

DIEPAD SOLDERED TO PCB PER JESD51-5

EL7554