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TLV62568 Datasheet(PDF) 5 Page - Texas Instruments |
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TLV62568 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 26 page 5 TLV62568, TLV62568P www.ti.com SLVSD89A – NOVEMBER 2016 – REVISED APRIL 2017 Product Folder Links: TLV62568 TLV62568P Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated 6.5 Electrical Characteristics VIN = 5.0 V, TJ = 25°C, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Quiescent current into VIN pin Not switching 35 uA ISD Shutdown current into VIN pin EN = 0 V 0.1 2 µA VUVLO Under voltage lock out VIN falling 2.3 2.45 V Under voltage lock out hysteresis 100 mV TJSD Thermal shutdown threshold Junction temperature rising 150 °C Junction temperature falling 130 LOGIC INTERFACE VIH High-level input voltage at EN pin 2.5 V ≤ VIN ≤ 5.5 V 1.2 0.95 V VIL Low-level input voltage at EN pin 2.5 V ≤ VIN ≤ 5.5 V 0.85 0.4 V tSS Soft startup time TLV62568DBV 700 µs TLV62568DRL, TLV62568PDRL 900 VPG Power good threshold, TLV62568P VFB rising, referenced to VFB nominal 95% VFB falling, referenced to VFB nominal 90% VPG,OL Power good low-level output voltage ISINK = 1 mA 0.4 V IPG,LKG Input leakage current into PG pin VPG = 5.0 V 0.01 µA tPG,DLY Power good delay time VFB falling 40 µs OUTPUT VFB Feedback regulation voltage 0.588 0.6 0.612 V RDS(on) High-side FET on resistance 150 m Ω Low-side FET on resistance 100 ILIM High-side FET current limit 1.5 A fSW Switching frequency VOUT = 1.8 V 1.5 MHz |
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