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TLV62569DRLR Datasheet(PDF) 4 Page - Texas Instruments |
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TLV62569DRLR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 25 page 4 TLV62569, TLV62569P SLVSDG1C – DECEMBER 2016 – REVISED OCTOBER 2017 www.ti.com Product Folder Links: TLV62569 TLV62569P Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V (1) Refer to the Application and Implementation section for further information. 6.3 Recommended Operating Conditions (1) MIN TYP MAX UNIT VIN Input voltage 2.5 5.5 V VOUT Output voltage 0.6 VIN V IOUT Output current 0 2 A TJ Operating junction temperature –40 125 °C ISINK_PG Sink current at PG pin 1 mA (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.4 Thermal Information THERMAL METRIC(1) DBV (5 Pins) DDC (6 Pins) DRL (6 Pins) UNIT RθJA Junction-to-ambient thermal resistance 188.2 106.2 146.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 137.5 52.9 51.0 °C/W RθJB Junction-to-board thermal resistance 41.2 31.2 27.0 °C/W ψJT Junction-to-top characterization parameter 31.4 11.3 2.2 °C/W ψJB Junction-to-board characterization parameter 40.6 31.6 27.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W 6.5 Electrical Characteristics VIN = 5.0 V, TJ = 25°C, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Quiescent current into VIN pin Not switching 35 uA ISD Shutdown current into VIN pin EN = 0 V 0.1 2 µA VUVLO Under voltage lock out VIN falling 2.3 2.45 V Under voltage lock out hysteresis 100 mV TJSD Thermal shutdown Junction temperature rising 150 °C Junction temperature falling 130 LOGIC INTERFACE VIH High-level threshold at EN pin 2.5 V ≤ VIN ≤ 5.5 V 0.95 1.2 V VIL Low-level threshold at EN pin 2.5 V ≤ VIN ≤ 5.5 V 0.4 0.85 V tSS Soft startup time TLV62569DBV 800 µs TLV62569PDDC, TLV62569DRL, TLV62569PDRL 900 VPG Power good threshold VFB rising, referenced to VFB nominal 95% VFB falling, referenced to VFB nominal 90% VPG,OL Power good low-level output voltage ISINK = 1 mA 0.4 V IPG,LKG Input leakage current into PG pin VPG = 5.0 V 0.01 µA tPG,DLY Power good delay time VFB falling 40 µs OUTPUT VFB Feedback regulation voltage 0.588 0.6 0.612 V |
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