PG

1

2

3

6

5

4

EN

SW

GND

VIN

FB

NC/PG

1

2

3

6

5

4

EN

SW

GND VIN

FB

1

2

3

5

4

EN

SW

GND

VIN

FB

SOT23-5

DBV Package

(Top View)

SOT23-6

DDC Package

(Top View)

SOT563-6

DRL Package

(Top View)

3

TLV62568, TLV62568P

www.ti.com

SLVSD89A – NOVEMBER 2016 – REVISED APRIL 2017

Product Folder Links: TLV62568 TLV62568P

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Copyright © 2016–2017, Texas Instruments Incorporated

5 Pin Configuration and Functions

Pin Functions

PIN NUMBER

I/O/PWR

DESCRIPTION

NAME

SOT23-5

SOT23-6

SOT563-6

EN

1

1

5

I

Device enable logic input. Logic high enables the device, logic low disables

the device and turns it into shutdown. Do not leave floating.

GND

2

2

2

PWR

Ground pin.

SW

3

3

4

PWR

Switch pin connected to the internal FET switches and inductor terminal.

Connect the inductor of the output filter to this pin.

VIN

4

4

3

PWR

Power supply voltage input.

PG

-

5

6

O

Power good open drain output pin for TLV62568P. The pull-up resistor should

not be connected to any voltage higher than 5.5V. If it's not used, leave the

pin floating.

FB

5

6

1

I

Feedback pin for the internal control loop. Connect this pin to an external

feedback divider.

NC

-

-

6

O

No connection pin for TLV62568DRL. The pin can be connected to the output.

Or leave it floating.

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Functional operation of the

device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to

absolute–maximum–rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to network ground terminal.

(3)

While switching.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

VIN, EN, PG

–0.3

6

V

SW (DC)

–0.3

V

–3.0

9

V

FB

–0.3

5.5

V

–40

150

°C

–65

150

°C