5

TPS63710

www.ti.com

SLVSD44 – SEPTEMBER 2017

Product Folder Links: TPS63710

Submit Documentation Feedback

Copyright © 2017, Texas Instruments Incorporated

(1)

dc voltage applied. Therefore, the nominal capacitor value needs to be larger than the minimum values given in the table. Please check

the manufacturer´s dc bias curves for the effective capacitance vs dc voltage applied.

(2)

If a maximum output current below 1A is required, the capacitance can be reduced accordingly. See the application section for details.

(3)

The maximum value also includes dc bias at the nominal operating voltage. During start-up when the voltage is 0 V, the effective

capacitance can be higher. Please see the application section for details.

6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

Supply Voltage Range

3.1

14

V

-1

1

V/µs

-0.1

0.1

V/µs

Output Current

duty cycle

≤ 70%

-1

0

A

L

Effective Inductance

1.5

2.2

6.2

µH

15

44

100

µF

22

44

100

µF

µF

Effective Capacitance on the CP pin required for full output current at

≤ 70% duty

4

4.7

µF

0.08

0.22

1

µF

0.01

10

µF

R

Total resistance for R1 + R2 from VREF to GND

100

500

kΩ

Operating Junction Temperature

-40

125

°C

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.4 Thermal Information

TPS63710

UNIT

DRR (WSON)

12 PINS

Junction-to-ambient thermal resistance

44.3

°C/W

Junction-to-case (top) thermal resistance

47.7

°C/W

Junction-to-board thermal resistance

18.9

°C/W

Junction-to-top characterization parameter

0.4

°C/W

Junction-to-board characterization parameter

19.1

°C/W

Junction-to-case (bottom) thermal resistance

5.8

°C/W