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UCC24612-1DBVT Datasheet(PDF) 6 Page - Texas Instruments |
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UCC24612-1DBVT Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 40 page  6 UCC24612 SLUSCM5 – AUGUST 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 6.5 Electrical Characteristics At VDD = 12 VDC, CVG = 0 pF, CREG = 2.2 µF, −40°C ≤ TJ = TA ≤ +125°C, all voltages are with respect to VS, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BIAS SUPPLY IVDDSTART VDD current, REG undervoltage VDD = 4 V, VD = 0 V 120 μA IVDDRUN VDD current, run VDD = 12 V 0.95 mA VDD = 5 V 0.9 mA IVDDSTBY VDD current, standby mode VDD = 12 V 390 μA VDD = 5 V 320 μA UNDERVOLTAGE LOCKOUT (UVLO) VREGON REG turnon threshold Turnon detected by 4.5 V VREGOFF REG turnoff threshold Turnoff detected by 4 V VREGHYST UVLO hysteresis VREGHYST = VREGON – VREGOFF 0.5 V MOSFET VOLTAGE SENSING VTHVGON GATE turnon threshold VD falling -226 mV VTHVGOFF GATE turnoff threshold VD rising -10 mV VTHREGLO Low level regulation threshold -50 mV VTHREGCCM High level regulation threshold for CCM -150 mV VTHARM Gate re-arming threshold 0.5 V IVDBIAS VD pin bias current VD = –100 mV -0.9 µA GATE DRIVER RSOURCE VG pullup resistance IVG = –20 mA, VDD = 12 V 5.7 Ω RSINK VG pulldown resistance IVG = 100 mA, VDD = 12 V 0.62 Ω VGH VG clamp level 9.4 V VGL VG output low voltage IVG = 100 mA, VDD = 12 V 60 mV VOLGUV VG output low voltage in UVLO IVG = 25 mA, VDD = 4 V 0.7 V IVGPU Gate driver maximum source current 1 A IVGPD Gate driver maximum sink current 4 A REG SUPPLY VREG REG pin regulation level VDD = 12 V 9.42 V VREGLG Load regulation on REG VDD = 12 V, ILOAD_REG= 10 mA to 0 mA 0.015 V VREGDO REG drop out on passthrough mode VDD = 5 V, ILOAD_REG= 10 mA 0.28 V IREGSC REG short circuit current VDD = 12 V, VREG = 0 V 5.2 mA IREGLIM REG current limit VDD = 12 V, VREG = 8V 42 mA |
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