Copyright © 2017, Texas Instruments Incorporated

REG

VDD

VD

START

TSD

VG

VS

Adaptive TOFF

& DCM ring rejection

(-220mV)

S

Q

Q

R

(-10mV)

Minimum

TON

(-50mV)

Prop-DRV

threshold

9.5-V Linear

Regulator

REG

UVLO

POWER & FAULT

MANGEMENT

PROPORTION

GATE DRIVE

CONTROL

GATE

DRIVER

9

UCC24612

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SLUSCM5 – AUGUST 2017

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Copyright © 2017, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The UCC24612 synchronous rectifier (SR) controller uses drain-to-source voltage sensing to determine the SR

the conduction loss while allowing SR to pre-turn off to operate in CCM mode. The extremely fast turn off

comparator and driving circuit allows the fast turn off of SR MOSFET, even in CCM condition. Fixed 350-ns

minimum on time allows the controller effectively driving the SR operating up to 1-MHz switching frequency. The

adaptive minimum off time control simplifies the design, making the controller suitable to be used in wide

applications and switching frequencies, while immune to the noises caused by the parasitic ringing. To minimize

the standby power, automatic light-load mode disables the GATE pulses when the average switching frequency

of the converter becomes lower than 12 kHz. When the load increases such that the average switching

frequency becomes above 15 kHz, the controller resumes normal SR operation. The wide VDD range and gate

driver clamp makes the controller ideal for wide output voltage range such as USB-PD applications.

7.2 Functional Block Diagram