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ICL7136CPL Datasheet(PDF) 6 Page - Intersil Corporation |
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ICL7136CPL Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 15 page 6 FN3086.6 July 21, 2005 Detailed Description Analog Section Figure 2 shows the Analog Section for the ICL7136. Each measurement cycle is divided into four phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de- integrate (DE), (4) zero integrate (ZI). Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A- Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10 µV. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low Pin Descriptions PIN NUMBER NAME FUNCTION DESCRIPTION 40 PIN DIP 44 PIN FLATPACK 1 8 V+ Supply Power Supply. 2 9 D1 Output Driver Pin for Segment “D” of the display units digit. 3 10 C1 Output Driver Pin for Segment “C” of the display units digit. 4 11 B1 Output Driver Pin for Segment “B” of the display units digit. 5 12 A1 Output Driver Pin for Segment “A” of the display units digit. 6 13 F1 Output Driver Pin for Segment “F” of the display units digit. 7 14 G1 Output Driver Pin for Segment “G” of the display units digit. 8 15 E1 Output Driver Pin for Segment “E” of the display units digit. 9 16 D2 Output Driver Pin for Segment “D” of the display tens digit. 10 17 C2 Output Driver Pin for Segment “C” of the display tens digit. 11 18 B2 Output Driver Pin for Segment “B” of the display tens digit. 12 19 A2 Output Driver Pin for Segment “A” of the display tens digit. 13 20 F2 Output Driver Pin for Segment “F” of the display tens digit. 14 21 E2 Output Driver Pin for Segment “E” of the display tens digit. 15 22 D3 Output Driver pin for segment “D” of the display hundreds digit. 16 23 B3 Output Driver pin for segment “B” of the display hundreds digit. 17 24 F3 Output Driver pin for segment “F” of the display hundreds digit. 18 25 E3 Output Driver pin for segment “E” of the display hundreds digit. 19 26 AB4 Output Driver pin for both “A” and “B” segments of the display thousands digit. 20 27 POL Output Driver pin for the negative sign of the display. 21 28 BP/GND Output Driver pin for the LCD backplane/Power Supply Ground. 22 29 G3 Output Driver pin for segment “G” of the display hundreds digit. 23 30 A3 Output Driver pin for segment “A” of the display hundreds digit. 24 31 C3 Output Driver pin for segment “C” of the display hundreds digit. 25 32 G2 Output Driver pin for segment “G” of the display tens digit. 26 34 V- Supply Negative power supply. 27 35 INT Output Integrator amplifier output. To be connected to integrating capacitor. 28 36 BUFF Output Input buffer amplifier output. To be connected to integrating resistor. 29 37 A-Z Input Integrator amplifier input. To be connected to auto-zero capacitor. 30 31 38 39 IN LO IN HI Input Differential inputs. To be connected to input voltage to be measured. LO and HI designators are for reference and do not imply that LO should be connected to lower potential, e.g., for negative inputs IN LO has a higher potential than IN HI. 32 40 COMMON Supply/ Output Internal voltage reference output. 33 34 41 42 CREF- CREF+ Connection pins for reference capacitor. 35 36 43 44 REF LO REF HI Input Input pins for reference voltage to the device. REF HI should be positive reference to REF LO. 37 3 TEST Input Display test. Turns on all segments when tied to V+. 38 39 40 4 6 7 OSC3 OSC2 OSC1 Output Output Input Device clock generator circuit connection pins. ICL7136 |
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