IS61LV256

6

Integrated Circuit Solution Inc.

SR004-0D

AC WAVE.ORMS

DATA UNDEFINED

VALID ADDRESS

HIGH-Z

ADDRESS

CE

WE

-8 ns

-10 ns

-12 ns

-15 ns

-20 ns

Symbol Parameter

Min. Max.

Min. Max.

Min. Max.

Min. Max.

Min. Max.

Unit

Write Cycle Time

8

—

10 —

12 —

15 —

20 —

ns

CE to Write End

7

—

8

—

8

—

10 —

12 —

ns

Address Setup Time

7

—

8

—

8

—

10 —

12 —

ns

to Write End

Address Hold

0

—

0

—

0

—

0

—

0

—

ns

from Write End

Address Setup Time

0

—

0

—

0

—

0

—

0

—

ns

7

—

10 —

12 —

15 —

20 —

ns

6.5 —

7

—

8

—

10 —

12 —

ns

Data Setup to Write End

4.5 —

5

—

6

—

7

—

10 —

ns

Data Hold from Write End

0

—

0

—

0

—

0

—

0

—

ns

— 3.5

—

4

—

6

—

7

—

7

ns

0

—

0

—

0

—

0

—

0

—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse

levels of 0 to 3.0V and output loading specified in .igure 1.

2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid

states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and

Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.

3. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%

tested.