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AD7172-4BCPZ Datasheet(HTML) 6 Page - Analog Devices

Part No. AD7172-4BCPZ
Description  ADC with True Rail-to-Rail Buffers
Download  62 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7172-4BCPZ Datasheet(HTML) 6 Page - Analog Devices

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Data Sheet
AD7172-4
Rev. B | Page 5 of 61
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
GPIO (GPIO0, GPIO1)
With respect to AVSS
Input Mode Leakage Current1
−10
+10
μA
Floating State Output
Capacitance
5
pF
Output Voltage1
High, VOH
ISOURCE = 200 μA
AVSS + 4
V
Low, VOL
ISINK = 800 μA
AVSS + 0.4
V
Input Voltage1
High, VIH
AVSS + 3
V
Low, VIL
AVSS + 0.7
V
CLOCK
Internal Clock
Frequency
2
MHz
Accuracy
−2.6%
+2.5%
%
Duty Cycle
50
%
Output Voltage
Low, VOL
0.4
V
High, VOH
0.8 × IOVDD
V
Crystal
Frequency
14
16
16.384
MHz
Startup Time
10
μs
External Clock (CLKIO)
2
2.048
MHz
Duty Cycle1
30
50
70
%
LOGIC INPUTS
Input Voltage1
High, VINH
2 V ≤ IOVDD < 2.3 V
0.65 × IOVDD
V
2.3 V ≤ IOVDD ≤ 5.5 V
0.7 × IOVDD
V
Low, VINL
2 V ≤ IOVDD < 2.3 V
0.35 × IOVDD
V
2.3 V ≤ IOVDD ≤ 5.5 V
0.7
V
Hysteresis1
IOVDD ≥ 2.7 V
0.08
0.25
V
IOVDD < 2.7 V
0.04
0.2
V
Leakage Currents
−10
+10
μA
LOGIC OUTPUT (DOUT/RDY)
Output Voltage1
High, VOH
IOVDD ≥ 4.5 V, ISOURCE = 1 mA
0.8 × IOVDD
V
2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 μA
0.8 × IOVDD
V
IOVDD < 2.7 V, ISOURCE = 200 μA
0.8 × IOVDD
V
Low, VOL
IOVDD ≥ 4.5 V, ISINK = 2 mA
0.4
V
2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA
0.4
V
IOVDD < 2.7 V, ISINK = 400 μA
0.4
V
Leakage Current
Floating state
−10
+10
μA
Output Capacitance
Floating state
10
pF
SYSTEM CALIBRATION1
Full-Scale (FS) Calibration Limit
1.05 × FS
V
Zero-Scale Calibration Limit
−1.05 × FS
V
Input Span
0.8 × FS
2.1 × FS
V
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 to AVSS
3.0
5.5
V
AVDD2 to AVSS
2
5.5
V
AVSS to DGND
−2.75
0
V
IOVDD to DGND
2
5.5
V
IOVDD to AVSS
For AVSS < DGND
6.35
V


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