 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9695BCPZRL7-1300 Datasheet(PDF) 10 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD9695BCPZRL7-1300 Datasheet(HTML) 10 Page - Analog Devices |
|
|
10 / 136 page  Data Sheet AD9695 Rev. 0 | Page 9 of 135 Parameter1 Analog Input Full Scale = 1.36 V p-p Analog Input Full Scale = 1.7 V p-p Analog Input Full Scale = 2.04 V p-p Unit Min Typ Max Min Typ Max Min Typ Max ANALOG INPUT BANDWIDTH, FULL POWER5 2 2 2 GHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Noise density is measured at a low analog input frequcency (10 MHz). 3 Crosstalk is measured at 10 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel. 4 The overrange condition is specified with 3 dB of the full-scale input range. 5 Full power bandwidth is the bandwidth of operation to achieve proper ADC performance. DIGITAL SPECIFICATIONS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS (AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speedgrade), DCS off (AD9695-625 speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade). Table 4. Parameter Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance LVDS/LVPECL Differential Input Voltage 400 800 1600 mV p-p Input Common-Mode Voltage 0.65 V Input Resistance (Differential) 32 kΩ Input Capacitance (Differential) 0.9 pF SYSREF INPUTS (SYSREF+, SYSREF−) Logic Compliance LVDS/LVPECL Differential Input Voltage 400 800 1800 mV p-p Input Common-Mode Voltage 0.65 2 V Input Resistance (Differential) 18 kΩ Input Capacitance (Differential) 1 pF LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0, FD_B/GPIO_B0) Logic Compliance CMOS Logic 1 Voltage 0.75 × SPIVDD V Logic 0 Voltage 0 0.35 × SPIVDD V Input Resistance 30 kΩ LOGIC OUTPUT (SDIO, FD_A, FD_B) Logic Compliance CMOS Logic 1 Voltage (IOH = 4 mA) SPIVDD − 0.45 V Logic 0 Voltage (IOL = 4 mA) 0 0.45 V SYNCIN INPUTS (SYNCINB−, SYNCINB+) Logic Compliance LVDS/LVPECL/CMOS Differential Input Voltage 400 800 1800 mV p-p Input Common-Mode Voltage 0.65 2 V Input Resistance (Differential) 18 kΩ Input Capacitance (Single-Ended per Pin) 1 pF DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3) Logic Compliance SST Differential Output Voltage 360 520 770 mV p-p Differential Termination Impedance 80 100 1200 Ω |
Similar Part No. - AD9695BCPZRL7-1300 |
|
Similar Description - AD9695BCPZRL7-1300 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
