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AD9625BBPZ-2.0 Datasheet(PDF) 4 Page - Analog Devices |
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AD9625BBPZ-2.0 Datasheet(HTML) 4 Page - Analog Devices |
4 / 74 page AD9625 Data Sheet Rev. C | Page 2 of 72 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Specifications .................................................................. 7 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 16 AD9625-2.0 ................................................................................. 17 AD9625-2.5 ................................................................................. 20 AD9625-2.6 ................................................................................. 24 Equivalent Test Circuits ................................................................. 27 Theory of Operation ...................................................................... 28 ADC Architecture ...................................................................... 28 Fast Detect ................................................................................... 28 Gain Threshold Operation........................................................ 28 Test Modes................................................................................... 29 Analog Input Considerations........................................................ 30 Differential Input Configurations ............................................ 30 Using the ADA4961 ................................................................... 30 DC Coupling ............................................................................... 32 Clock Input Considerations ...................................................... 32 Digital Downconverters (DDC) ................................................... 33 Frequency Synthesizer and Mixer ............................................ 33 Numerically Controlled Oscillator .......................................... 33 High Bandwidth Decimator ..................................................... 33 Low Bandwidth Decimator....................................................... 36 Digital Outputs ............................................................................... 37 Introduction to the JESD204B Interface ................................. 37 Functional Overview ................................................................. 37 JESD204B Link Establishment ................................................. 39 Physical Layer Output................................................................ 43 Scrambler..................................................................................... 43 Tail Bits ........................................................................................ 43 DDC Modes (Single and Dual) ................................................ 43 CheckSum ................................................................................... 44 8-Bit/10-Bit Encoder Control ................................................... 44 Initial Lane Alignment Sequence (ILAS)................................ 44 Lane Synchronization ................................................................ 45 JESD204B Application Layers .................................................. 48 Frame Alignment Character Insertion.................................... 51 Thermal Considerations............................................................ 51 Power Supply Considerations................................................... 51 Serial Port Interface (SPI).............................................................. 52 Configuration Using the SPI..................................................... 52 Hardware Interface..................................................................... 52 Memory Map .................................................................................. 53 Reading the Memory Map Register ......................................... 53 Memory Map Registers ............................................................. 53 Applications Information .............................................................. 71 Design Guidelines ...................................................................... 71 Power and Ground Recommendations ................................... 71 Clock Stability Considerations ................................................. 71 SPI Port ........................................................................................ 71 Outline Dimensions ....................................................................... 72 Ordering Guide .......................................................................... 72 |
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