Electronic Components Datasheet Search |
|
AD9655 Datasheet(PDF) 9 Page - Analog Devices |
|
AD9655 Datasheet(HTML) 9 Page - Analog Devices |
9 / 38 page AD9655 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted. Table 6. Parameter1, 2 Temperature Min Typ Max Unit CLOCK3 Input Clock Rate Full 20 1000 MHz Conversion Rate Full 20 125 MSPS Clock Pulse Width High (tEH) Full 4.00 ns Clock Pulse Width Low (tEL) Full 4.00 ns OUTPUT PARAMETERS3 Propagation Delay (tPD)4 Full (tSAMPLE/4) + 5 (tSAMPLE/4) + 6.1 (tSAMPLE/4) + 7 ns Rise Time (tR)5 (20% to 80%) Full 170 ps Fall Time (tF)5 (20% to 80%) Full 160 ps FCO Propagation Delay (tFCO)4 Full (tSAMPLE/4) + 5 (tSAMPLE/4) + 6.1 (tSAMPLE/4) + 7 ns DCO Propagation Delay (tCPD)4 Full tFCO + (tSAMPLE/16) + 0.2 ns DCO to Data Delay (tDATA)4, 6 Full (tSAMPLE/16) − 500 (tSAMPLE/16) + 100 ps FCO to DCO Delay (tFRAME)4, 7 Full (tSAMPLE/16) + 10 (tSAMPLE/16) + 330 ps Data to Data Skew Full ±37 ±80 ps Wake-Up Time (Standby) 25°C 250 ns Wake-Up Time (Power-Down)8 25°C 250 ms Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (tA)9 25°C 1 ns Aperture Uncertainty (Jitter, tJ5,9) 25°C 80 fs rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 The Output parameters can be adjusted via the SPI. The conversion rate is the clock rate after the divider. Valid for 2-lane operation. 4 tSAMPLE = tEH + tEL = 1/fS. tCPD, tDATA and tFRAME are adjustable with SPI Register 0x16. 5 This term does not appear in the Timing Diagrams section, which includes Figure 2 and Figure 3. 6 tDATA is the time from DCO rise or fall to output data rise or fall. 7 tFRAME is the time from FCO rise to DCO rise. 8 Wake-up time from power-down is defined as the time required to return to normal operation from SPI power-down mode. The value of 250 ms assumes a sample rate of 125 MSPS. About 31 × 106 sample clock cycles are required. 9 tA and tJ are with Register 0x09 = 0x04 (default, duty cycle stabilizer and clock divider are bypassed). TIMING SPECIFICATIONS Table 7. Parameter Description Limit Unit SPI TIMING REQUIREMENTS See Figure 68, unless otherwise noted tDS Setup time between the data and the rising edge of SCLK 4 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO1 Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns min tDIS_SDIO1 Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns min 1 This parameter is not shown in Figure 68. Rev. 0 | Page 8 of 37 |
Similar Part No. - AD9655 |
|
Similar Description - AD9655 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |