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AD9680BCPZ-1250 Datasheet(PDF) 11 Page - Analog Devices |
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AD9680BCPZ-1250 Datasheet(HTML) 11 Page - Analog Devices |
11 / 99 page Data Sheet AD9680 Rev. C | Page 9 of 97 SWITCHING SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate for each speed grade, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 4. AD9680-500 AD9680-820 AD9680-1000 AD9680-1250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit CLOCK Clock Rate (at CLK+/CLK− Pins) Full 0.3 4 0.3 4 0.3 4 0.3 4 GHz Maximum Sample Rate1 Full 500 820 1000 1250 MSPS Minimum Sample Rate2 Full 300 300 300 300 MSPS Clock Pulse Width High Full 1000 609.7 500 400 ps Clock Pulse Width Low Full 1000 609.7 500 400 ps OUTPUT PARAMETERS Unit Interval (UI)3 Full 80 200 80 121.95 80 100 80 80 ps Rise Time (tR) (20% to 80% into 100 Ω Load) 25°C 24 32 24 32 24 32 24 32 ps Fall Time (tF) (20% to 80% into 100 Ω Load) 25°C 24 32 24 32 24 32 24 32 ps PLL Lock Time 25°C 2 2 2 2 ms Data Rate per Channel (NRZ)4 25°C 3.125 5 12.5 3.125 8.2 12.5 3.125 10 12.5 3.1215 12.5 12.5 Gbps LATENCY5 Pipeline Latency Full 55 55 55 55 Clock cycles Fast Detect Latency Full 28 28 28 28 Clock cycles Wake-Up Time6 Standby 25°C 1 1 1 1 ms Power-Down 25°C 4 4 4 4 ms APERTURE Aperture Delay (tA) Full 530 530 530 530 ps Aperture Uncertainty (Jitter, tJ) Full 55 55 55 55 fS rms Out-of-Range Recovery Time Full 1 1 1 1 Clock cycles 1 The maximum sample rate is the clock rate after the divider. 2 The minimum sample rate operates at 300 MSPS with L = 2 or L = 1. 3 Baud rate = 1/UI. A subset of this range can be supported. 4 Default L = 4. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 4, M = 2, F = 1. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. |
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