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AD9690BCPZRL7-1000 Datasheet(PDF) 1 Page - Analog Devices |
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AD9690BCPZRL7-1000 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 79 page  14-Bit, 1 GSPS/500 MSPS JESD204B, Analog-to-Digital Converter Data Sheet AD9690 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES JESD204B (Subclass 1) coded serial digital outputs 2.0 W total power at 1 GSPS (default settings) 1.5 W total power at 500 MSPS (default settings) SFDR = 85 dBFS at 340 MHz, 80 dBFS at 985 MHz SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 985 MHz ENOB = 10.8 bits at 10 MHz DNL = ±0.5 LSB INL = ±2.5 LSB Noise density = −154 dBFS/Hz at 1 GSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation No missing codes Internal ADC voltage reference Flexible input range AD9690-1000: 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal) AD9690-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) Programmable termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 2 GHz usable analog input full power bandwidth Amplitude detect bits for efficient AGC implementation 2 integrated wideband digital processors 12-bit NCO, up to 4 cascaded half-band filters Differential clock input Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Small signal dither APPLICATIONS Communications Multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers Wideband digital predistortion FUNCTIONAL BLOCK DIAGRAM VIN+ VIN– CLK+ CLK– AD9690 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± ÷2 ÷4 SYSREF± CLOCK GENERATION 14 PDWN/ STBY SYNCINB± FD BUFFER JESD204B SUBCLASS 1 CONTROL V_1P0 ÷8 FAST DETECT AGND DRGND DGND SDIO SCLK CSB AVDD1 (1.25V) AVDD2 (2.5V) AVDD3 (3.3V) AVDD1_SR (1.25V) DVDD (1.25V) DRVDD (1.25V) SPIVDD (1.8V TO 3.3V) 4 ADC CORE SPI CONTROL DDC CONTROL REGISTERS Figure 1. PRODUCT HIGHLIGHTS 1. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. 2. Buffered inputs with programmable input termination eases filter design and implementation. 3. Two integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. 4. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. 5. Programmable fast overrange detection. 6. 9 mm × 9 mm, 64-lead LFCSP. |
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