AD9633

Data Sheet

Rev. B | Page 6 of 41

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 4.

Temp

Min

Typ

Max

Unit

Input Clock Rate

Full

10

1000

MHz

Full

10

80/105/125

MSPS

Full

6.25/4.76/4.00

ns

Full

6.25/4.76/4.00

ns

Full

1.5

2.3

3.1

ns

Full

300

ps

Full

300

ps

Full

1.5

2.3

3.1

ns

Full

ns

Full

ps

Full

ps

90

ps

Full

±50

±200

ps

Wake-Up Time (Standby)

25°C

250

ns

25°C

375

μs

Pipeline Latency

Full

16

Clock cycles

APERTURE

25°C

1

ns

25°C

135

fs rms

Out-of-Range Recovery Time

25°C

1

Clock cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.

4

The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section for the maximum conversion rate in one-lane output

mode.

5

6

Wake-up time is defined as the time required to return to normal operation from power-down mode.