 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD6650BBC1 Datasheet(PDF) 7 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD6650BBC1 Datasheet(HTML) 7 Page - Analog Devices |
|
|
7 / 28 page  Preliminary Technical Data AD6650 REV. PrJ 02/27/2003 7 MICROPROCESSOR PORT TIMING CHARACTERISTICS1 MICROPROCESSOR PORT, MODE INM (MODE=0) Temp Test Level Min AD6650 Typ Max Units MODE INM Write Timing: tSC tHC tHWR Control3 to ↑CLK Setup Time Control3 to ↑CLK Hold Time /WR(RW) to RDY(/DTACK) Hold Time Full Full Full IV IV IV 5.5 1.0 8.0 ns ns ns tSAM Address/Data to /WR(RW) Setup Time Full IV -0.5 ns tHAM Address/Data to RDY(/DTACK) Hold Time Full IV 7.0 ns tDRDY /WR(RW) to RDY(/DTACK) Delay Full IV 4.0 ns tACC /WR(RW) to RDY(/DTACK) High Delay Full IV 4*tCLK 5*tCLK ns MODE INM Read Timing: tSC tHC tSAM Control3 to ↑CLK Setup Time Control3 to ↑CLK Hold Time Address to /RD(/DS) Setup Time Full Full Full IV IV IV 4.0 2.0 0.0 ns ns ns tHAM Address to Data Hold Time Full IV 7.0 ns tZD Data Tri-state Delay Full IV ns tDD RDY(/DTACK) to Data Delay Full IV ns tDRDY /RD(/DS) to RDY(/DTACK) Delay Full IV 4.0 ns tACC /RD(/DS) to RDY(/DTACK) High Delay Full IV 4*tCLK 7*tCLK ns MICROPROCESSOR PORT, MODE MNM (MODE=1) Temp Test Level Min AD6650 Typ Max Units MODE MNM Write Timing: tSC tHC tHDS Control3 to ↑CLK Setup Time Control3 to ↑CLK Hold Time /DS(/RD) to /DTACK(RDY) Hold Time Full Full Full IV IV IV 5.5 1.0 8.0 ns ns ns tHRW RW(/WR) to /DTACK(RDY) Hold Time Full IV 8.0 ns tSAM Address/Data To RW(/WR) Setup Time Full IV -0.5 ns tHAM Address/Data to RW(/WR) Hold Time Full IV 7.0 ns tDDTACK /DS(/RD) to /DTACK(RDY) Delay Full IV ns tACC RW(/WR) to /DTACK(RDY) Low Delay Full IV 4*tCLK 5*tCLK ns MODE MNM Read Timing: tSC tHC tHDS Control3 to ↑CLK Setup Time Control3 to ↑CLK Hold Time /DS(/RD) to /DTACK(RDY) Hold Time Full Full Full IV IV IV 4.0 2.0 8.0 ns ns ns tSAM Address to /DS(/RD) Setup Time Full IV 0.0 ns tHAM Address to Data Hold Time Full IV 7.0 ns tZD Data Tri-State Delay Full IV ns tDD /DTACK(RDY) to Data Delay Full IV ns tDDTACK /DS(/RD) to /DTACK(RDY) Delay Full IV ns tACC /DS(/RD) to /DTACK(RDY) Low Delay Full IV 4*tCLK 7*tCLK ns MODE I2C Timing: tDSCL ↑SCL to SDA Delay Full IV 61 ns tDSDA SDA to ↑SCL Delay Full IV 57 ns tSSCL 5 ↑CLK to ↑SCL Delay Full IV 5 ns 1All Timing Specifications valid over VDD range of 3.0V to 3.6V and VDDIO range of 3.0V to 3.6V. 2The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both channels (0, 1) 3Specification pertains to control signals: RW, (/WR), /DS, (/RD), /CS 4(CLOAD=40pF on all outputs unless otherwise specified) 5There is no hold time for SDA because as this waits for a negative transition (↓) on SCL to transition. |
Similar Part No. - AD6650BBC1 |
|
Similar Description - AD6650BBC1 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
