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PS4011C-0200

Advanced Hardware Architectures, Inc.

1.2.1

DEFINITION OF CORRECTION TERMS

*

For every 2 check bytes, the AHA4011C can correct either 2 erasures or 1 error.

** An erasure is detected by a parity detector or a signal dropout detector. The presence of an erasure is indicated

by asserting the ERASE signal when the erased byte is clocked into the AHA4011C.

2.0

FUNCTIONAL DESCRIPTION

This section describes an architectural

overview of the chip and its many functions,

features and operations. The block diagram for the

chip shows the Reed-Solomon ECC module, the

Input and Output Buffers, and their associated

control. All input and output data are clocked on the

rising edge of CLK.

2.1

FUNCTIONAL OVERVIEW

The AHA4011C Reed-Solomon codec

(coder/decoder) is a member of the AHA PerFEC™

family of high speed forward error correction (FEC)

devices. This single chip, three-layer metal, CMOS

device can operate in encode, decode or pass-

through modes.

The ECC core implements a full error

correcting Reed-Solomon decoder. This code is

capable of correcting up to 10 (t

=10) byte-errors or

20 (t

=10) erasures in a RS block.

The ECC core has three phases of operation:

Data In, Calculation and Data Out. Data to be

processed is first input into a single ported Input

Buffer using a control signal DSIN. ECC core

arbitrates for the input data out of the Input Buffer.

ECC core has access to the Input Buffer on clock

edges where DSIN is not asserted.

Each block is processed within the ECC core

and calculations are made. The entire block is

processed through the ECC core, and transferred

into the Output Buffer. The device asserts RDYON

signal and holds active until the Output Buffer is

completely emptied.

The ECC core loads the Output Buffer in

reverse order for either operation. Data may be

strobed out of the device in forward or reverse order.

If forward order is desired, output data cannot be

strobed out of the device until the entire block has

been loaded into the Output Buffer.

TERM

NAME

(other references)

DEFINITION

RANGE

(number of bytes)

K

Message Length (user

data or message bytes)

Number of user data symbols in one message

block. Size of a symbol in AHA4011C is 8-bits.

Message length is K

= N − R. The first message

1 through 253

(1, 2, 3, 4 . . . 253)

R

Check Symbols

(parity or redundancy)

Symbols appended to the user data to detect and

correct errors. The number of check symbols

required in a system is R

≥ E + 2e.* The first check

2 through 20 in

increments of 1

(2, 3, 4 . . . 20)

N

Codeword Length

(block length)

Sum of message and check symbols. N

= K + R. 3 through 255

(3, 4, 5, 6 . . . 255)

t

Error Corrections

Maximum number of error corrections performed

by the device. The value is t = Integer

.

1 through 10

(1, 2, 3 . . . 10)

P

Error Threshold

The threshold limit to determine uncorrectability

of a Codeword and the number of check bytes

allocated for correction-only purposes (not for

detection).

2 through 20

(2, 3, 4 . . . 20)

e

Number of Errors

An error is defined as an erroneous byte whose

correct value and position within the message

block are both unknown.

0 through N

E

Number of Erasures

An erasure is defined as an error whose position is

known within the message block.**

0 through N

G

Burden of Correction

A measure of the burden of correction being

placed on the capabilities of the device for that

message block. The value G

= 2e + E.

0 through R

NK

–

2

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