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CLC408AJP Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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CLC408AJP Datasheet(HTML) 8 Page - National Semiconductor (TI) |
8 / 12 page http://www.national.com 8 Unity gain applications are limited by the Common-Mode Input Range. At greater non-inverting gains, the Output Voltage Range becomes the limiting factor. Inverting gain applications are limited by the Output Voltage Range (and by the previous amplifier’s ability to drive Rg). For transimpedance gain applications, the sum of the input currents injected at the inverting input pin of the op amp needs to be: , where Vmax is the Output Voltage Range (see the DC Gain (transimpedance) sub-section for details). The equivalent output load needs to be large enough so that the output current can produce the required out- put voltage swing. See the DC Design (output loading) sub-section for details. Dynamic Range (noise) The output noise defines the lower end of the CLC408’s useful dynamic range. Reduce the value of resistors in the circuit to reduce noise. See the App Note Noise Design of CFB Op Amp Circuits for more details. Our SPICE models support noise simulations. Dynamic Range (distortion) The distortion plots in the Typical Performance Characteristics section show distortion as a function of load resistance, frequency, and output amplitude. Distortion places an upper limit on the CLC408’s dynamic range. The CLC408’s output stage combines a voltage buffer with a complementary common emitter current source. The interaction between the buffer and the current source produces a small amount of crossover distortion. This distortion mechanism dominates at low output swing and low resistance loads. To avoid this type of distortion, use the CLC408 at high output swing. Realized output distortion is highly dependent upon the external circuit. Some of the common external circuit choices that can improve distortion are: s Short and equal return paths from the load to the supplies s De-coupling capacitors of the correct value s Higher load resistance Printed Circuit Board Layout High frequency op amp performance is strongly dependent on proper layout, proper resistive termination and adequate power supply decoupling. The most important layout points to follow are: s Use a ground plane s Bypass power supply pins with: s monolithic capacitors of about 0.1 µF place less than 0.1” (3mm) from the pin s tantalum capacitors of about 6.8 µF for large signal current swings or improved power supply noise rejection; we recommend a minimum of 2.2 µF for any circuit s Minimize trace and lead lengths for components between the inverting and output pins s Remove ground plane underneath the amplifier package and 0.1” (3mm) from all input/output pads s For prototyping, use flush-mount printed circuit board pins; never use high profile DIP sockets. Evaluation Board Separate evaluation boards are available for proto-typing and measurements. Additional information is available in the evaluation board literature. SPICE Models SPICE models provide a means to evaluate op amp designs. Free SPICE models are available that: s Support Berkeley SPICE 2G and its many derivatives s Reproduce typical DC, AC, Transient, and Noise performance s Support room temperature simulations The readme file that accompanies the models lists the released models, and provides a list of modeled parameters. The application note Simulation SPICE Models for Comlinear’s Op Amps contains schematics and detailed information. The circuit shown in the Typical Application schematic on the front page operates as a full duplex cable driver which allows simultaneous transmission and reception of signals on one transmission line. The circuit on either side of the transmission line uses the CLC408 as a cable driver, and the CLC426 as a receiver. VoA is an attenuated version of VinA, while VoB is an attenuated version of VinB. Rm1 is used to match the transmission line. Rf2 and Rg2 set the DC gain of the CLC426, which is used in a differ- ence mode. Rt2 provides good CMRR and DC offset. The CLC408 is shown in a unity gain configuration because it consumes the least power of any gain, for a given load. For proper operation we need Rf2 = Rg2. The receiver output voltages are: where A is the attenuation of the cable, Zo(408)(jω) is the output impedance of the CLC408 (see the Closed-Loop Output Resistance plot), and |Zo(408)(jω)| << Rm1. I V R in max f ≤ CLC408 Applications VV A V 2 1 R R Z(j ) R outA(B) inA(B) inB(A) f2 g2 o(408) m1 ≈⋅ + ⋅ − + ω |
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