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AD9640ABCPZ-105 Datasheet(PDF) 7 Page - Analog Devices |
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AD9640ABCPZ-105 Datasheet(HTML) 7 Page - Analog Devices |
7 / 54 page AD9640 Rev. B | Page 5 of 52 SPECIFICATIONS ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 1. Parameter Temperature AD9640ABCPZ- 80/AD9640BCPZ-80 AD9640ABCPZ- 105/AD9640BCPZ-105 Unit Min Typ Max Min Typ Max RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0.3 ±0.6 % FSR Gain Error Full ±0.2 ±3.0 ±0.2 ±3.0 % FSR Differential Nonlinearity (DNL)1 Full ±0.9 ±0.9 LSB 25°C ±0.4 ±0.4 LSB Integral Nonlinearity (INL)1 Full ±5.0 ±5.0 LSB 25°C ±2.0 ±2.0 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.3 ±0.6 ±0.4 ±0.7 % FSR Gain Error Full ±0.1 ±0.5 ±0.1 ±0.5 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±2 ±15 ±2 ±15 mV Load Regulation @ 1.0 mA Full 7 7 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 1.3 1.3 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance2 Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES Supply Voltage AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current IAVDD1, 3 Full 233 277 310 371 mA IDVDD1, 3 Full 26 34 mA IDRVDD1 (3.3 V CMOS) Full 27 35 mA IDRVDD1 (1.8 V CMOS) Full 12 18 mA IDRVDD1 (1.8 V LVDS) Full 54 55 mA POWER CONSUMPTION DC Input Full 452 492 603 657 mW Sine Wave Input1 (DRVDD = 1.8 V) Full 487 645 mW Sine Wave Input1 (DRVDD = 3.3 V) Full 550 730 mW Standby Power4 Full 52 68 mW Power-Down Power Full 2.5 6 2.5 6 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins (CLK+, CLK −) inactive (set to AVDD or AGND). |
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