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AD9229 Datasheet(PDF) 1 Page - Analog Devices |
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AD9229 Datasheet(HTML) 1 Page - Analog Devices |
1 / 41 page Quad, 12-Bit, 50/65 MSPS, Serial, LVDS, 3 V A/D Converter AD9229 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005–2010 Analog Devices, Inc. All rights reserved. FEATURES Four ADCs in 1 package Serial LVDS digital output data rates to 780 Mbps (ANSI-644) Data and frame clock outputs SNR = 69.5 dB (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical) 400 MHz full power analog bandwidth Power dissipation 1,350 mW at 65 MSPS 985 mW at 50 MSPS 1 V p-p to 2 V p-p input voltage range 3.0 V supply operation Power-down mode Digital test pattern enable for timing alignments APPLICATIONS Digital beam-forming systems for ultrasound Wireless and wired broadband communications Communication test equipment FUNCTIONAL BLOCK DIAGRAM AD9229 12 12 12 12 VIN+A VIN–A D+A D–A SHA PIPELINE ADC SERIAL LVDS DATA RATE MULTIPLIER REF SELECT VIN+B VIN–B D+B D–B SHA PIPELINE ADC SERIAL LVDS VIN+C VIN–C D+C D–C SHA PIPELINE ADC SERIAL LVDS VIN+D VIN–D VREF SENSE D+D D–D 0.5V FCO+ FCO– DCO+ DCO– SHA PIPELINE ADC SERIAL LVDS REFT REFB AGND CLK LVDSBIAS PDWN DTP DRVDD DRGND Figure 1. GENERAL DESCRIPTION The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at up to a 65 MSPS conversion rate and is optimized for outstanding dynamic performance in applications where a small package size is critical. The ADC requires a single 3 V power supply and TTL-/CMOS- compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Power-down is supported and typically consumes 3 mW when enabled. Fabricated with an advanced CMOS process, the AD9229 is available in a Pb-free, 48-lead LFCSP package. It is specified over the industrial temperature range of –40°C to +85°C. PRODUCT HIGHLIGHTS 1. Four ADCs are contained in a small, space-saving package. 2. A data clock out (DCO) is provided, which operates up to 390 MHz and supports double-data rate operation (DDR). 3. The outputs of each ADC are serialized LVDS with data rates up to 780 Mbps (12 bits × 65 MSPS). 4. The AD9229 operates from a single 3.0 V power supply. 5. Packaged in a Pb-free, 48-lead LFCSP package. 6. The internal clock duty cycle stabilizer maintains performance over a wide range of input clock duty cycles. |
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